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Comparator Design for Delta Sigma Modulator

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IJCA Proceedings on International Conference on Emerging Trends in Technology and Applied Sciences
© 2015 by IJCA Journal
ICETTAS 2015 - Number 3
Year of Publication: 2015
Authors:
Pinka Abraham
Jayakrishnan K. R
Shahana T. K

Pinka Abraham, Jayakrishnan K.r and Shahana T.k. Article: Comparator Design for Delta Sigma Modulator. IJCA Proceedings on International Conference on Emerging Trends in Technology and Applied Sciences ICETTAS 2015(3):16-20, September 2015. Full text available. BibTeX

@article{key:article,
	author = {Pinka Abraham and Jayakrishnan K.r and Shahana T.k},
	title = {Article: Comparator Design for Delta Sigma Modulator},
	journal = {IJCA Proceedings on International Conference on Emerging Trends in Technology and Applied Sciences},
	year = {2015},
	volume = {ICETTAS 2015},
	number = {3},
	pages = {16-20},
	month = {September},
	note = {Full text available}
}

Abstract

In wide band communication systems, low power and high speed ADCs forms the main building blocks. These ADCs are commonly seen in the front end of the radio frequency receivers. Comparators are used in these ADCs. A CMOS Comparator design, based on amplifier-push pull inverter circuit is elaborated in this paper, which is intended to be used as the 1-bit ADC required for the implementation of a first order Delta Sigma (??) A/D converter. This particular design for the comparator makes it faster and lowers the power dissipation. This design is realized in both 180 nm and 90 nm CMOS processes using Cadence Virtuoso platform and low power dissipation is found in 90 nm implementation with 1. 2 V supply voltage. In this work simulation results are reported and comparison of comparator in both technologies are observed

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