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Performance Analysis of High Speed Double Tail Dynamic Comparator
| International Conference on Innovations in Information, Embedded and Communication Systems |
| Foundation of Computer Science USA |
| ICIIECS - Number 3 |
| November 2014 |
| Authors: S.brundha, K.saranya, P.sampath |
| 40afa66f-4e7a-46de-9a85-09ea59c4f06a |
S.brundha, K.saranya, P.sampath . Performance Analysis of High Speed Double Tail Dynamic Comparator. International Conference on Innovations in Information, Embedded and Communication Systems. ICIIECS, 3 (November 2014), 1-5.
Abstract
In this paper, we present a performance comparison of existing clocked dynamic comparators. As delay is directly correlated with the submicron scaling, we investigate the performance of the above comparators in terms of delay and Power-Delay Product (PDP). PDP gives the average energy dissipated by the comparator for a single comparison. Simulation results using Mentor Graphics revealed better performance of High Speed Dynamic Comparator (HSDC) compared to conventional clocked comparators in 180nm, 250nm and 350nm technologies. Implementation results reveal that high speed dynamic comparator has energy dissipation of 25. 14% less compared to the best of the designs used for comparison when operated at 50 MHz.
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