International Conference on Innovations in Information, Embedded and Communication Systems |
Foundation of Computer Science USA |
ICIIECS - Number 3 |
November 2014 |
Authors: M.mano, K.rekha Swathi Sri, G.selva Priya |
efe2eda5-d9b8-4ded-b963-5b6975f4cba0 |
M.mano, K.rekha Swathi Sri, G.selva Priya . Masked Advanced Encryption Standard for Area Optimization. International Conference on Innovations in Information, Embedded and Communication Systems. ICIIECS, 3 (November 2014), 28-32.
The Advanced Encryption Standard (AES) is a symmetric-key block cipher published by the National Institute of Standards and Technology (NIST)[1]. In order to protect data, a high throughput masked Advanced Encryption Standard (AES) engine is used. The masked AES engine uses the unrolling technique which requires extremely large field programmable gate array (FPGA) resources. The area for a masked AES with an unrolled structure is optimized. The mapping of operations from GF(28) to GF(24) as much as possible in order to optimize area. The number of mapping is reduced [GF(28) to GF(24)] and inverse mapping [GF(24) to GF(28)] operations of the masked SubBytes step from ten to one. In order to be compatible, the masked MixColumns, masked AddRoundKey, and masked ShiftRows including the redundant masking values are carried over GF(24). By moving, mapping and inverse mapping outside the masked AES's round function, area can be reduced by 20%.