CFP last date
20 May 2024
Reseach Article

Masked Advanced Encryption Standard for Area Optimization

Published on November 2014 by M.mano, K.rekha Swathi Sri, G.selva Priya
International Conference on Innovations in Information, Embedded and Communication Systems
Foundation of Computer Science USA
ICIIECS - Number 3
November 2014
Authors: M.mano, K.rekha Swathi Sri, G.selva Priya
efe2eda5-d9b8-4ded-b963-5b6975f4cba0

M.mano, K.rekha Swathi Sri, G.selva Priya . Masked Advanced Encryption Standard for Area Optimization. International Conference on Innovations in Information, Embedded and Communication Systems. ICIIECS, 3 (November 2014), 28-32.

@article{
author = { M.mano, K.rekha Swathi Sri, G.selva Priya },
title = { Masked Advanced Encryption Standard for Area Optimization },
journal = { International Conference on Innovations in Information, Embedded and Communication Systems },
issue_date = { November 2014 },
volume = { ICIIECS },
number = { 3 },
month = { November },
year = { 2014 },
issn = 0975-8887,
pages = { 28-32 },
numpages = 5,
url = { /proceedings/iciiecs/number3/18669-1489/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Innovations in Information, Embedded and Communication Systems
%A M.mano
%A K.rekha Swathi Sri
%A G.selva Priya
%T Masked Advanced Encryption Standard for Area Optimization
%J International Conference on Innovations in Information, Embedded and Communication Systems
%@ 0975-8887
%V ICIIECS
%N 3
%P 28-32
%D 2014
%I International Journal of Computer Applications
Abstract

The Advanced Encryption Standard (AES) is a symmetric-key block cipher published by the National Institute of Standards and Technology (NIST)[1]. In order to protect data, a high throughput masked Advanced Encryption Standard (AES) engine is used. The masked AES engine uses the unrolling technique which requires extremely large field programmable gate array (FPGA) resources. The area for a masked AES with an unrolled structure is optimized. The mapping of operations from GF(28) to GF(24) as much as possible in order to optimize area. The number of mapping is reduced [GF(28) to GF(24)] and inverse mapping [GF(24) to GF(28)] operations of the masked SubBytes step from ten to one. In order to be compatible, the masked MixColumns, masked AddRoundKey, and masked ShiftRows including the redundant masking values are carried over GF(24). By moving, mapping and inverse mapping outside the masked AES's round function, area can be reduced by 20%.

References
  1. NIST, "Advanced Encryption Standard (AES)," http://csrc. nist. gov/publications/fips/fips-197. pdf, Nov-2001.
  2. S. Mangard, N. Pramstaller, and E. Oswald, "Successfully attacking masked AES hardware implementations," in Proc. CHES LNCS, 2005, vol. 3659, pp. 157–171.
  3. E. Oswald, S. Mangard, N. Pramstaller, and V. Rijmen, "A side-channel analysis resistant description of the AESS-box," in Proc. FSE LNCS, Setubal, Potugal, 2005, vol. 3557, pp. 413–423.
  4. L. Goubin and J. Patarin, "DES and differential power analysis (the 'duplication' method)," in Proc. CHES LNCS, 1999, vol. 1717, pp. 158–172.
  5. S. Messerges, "Securing the AES finalists against power analysis attacks," in Proc. FSE LNCS, 2000, vol. 1978, pp. 150–164.
  6. K. Gaj and P. Chodowiec, "Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays," in Proc. CT-RSA LNCS, 2001, vol. 2020, pp. 84–99.
  7. J. Nechvatal et. al. , Report on the development of Advanced Encryption Standard, NIST publication, October 2, 2000.
  8. http://csrc. nist. gov/CryptoToolkit/aes/
  9. Hodjat and I. Verbauwhede, "A 21. 54 Gbits/s fully pipelined processor on FPGA," in Proc. IEEE 12th Annu. Symp. Field-Programm. Custom Comput. Mach. , 2004, pp. 308–309.
  10. NIST, "Data Encryption Standard (DES)," http://csrc. nist. gov/ publications/fips/fips46-3/fips46-3. pdf, Oct. 1999.
  11. Verbauwhede, P. Schaumont, and H. Kuo, "Design and Performance Testing of a 2. 29 gb/s Rijndael Processor," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 569-572, Mar. 2003.
  12. Daemen and V. Rijmen, The Design of Rijndael. Springer-Verlag, 2002.
  13. Z. Yuan, Y. Wang, J. Li, R. Li, and W. Zhao, "FPGA based optimization for masked AES implementation," in Proc. IEEE 54th Int. MWSCAS, Seoul, Korea, 2011, pp. 1–4
Index Terms

Computer Science
Information Sciences

Keywords

Advanced Encryption Standard (aes) Throughput Galios Field (gf) Masked Aes