The week's pick
Random Articles
Reseach Article
Certain Investigations on Power Performance in Nanoscale CMOS Digital Circuits with Low Leakage Design Techniques
| International Conference on Innovations in Information, Embedded and Communication Systems |
| Foundation of Computer Science USA |
| ICIIECS - Number 4 |
| November 2014 |
| Authors: Greeshma.v, R. Udaiya Kumar |
| d2956871-881e-48a5-b9c1-0bfb418356e3 |
Greeshma.v, R. Udaiya Kumar . Certain Investigations on Power Performance in Nanoscale CMOS Digital Circuits with Low Leakage Design Techniques. International Conference on Innovations in Information, Embedded and Communication Systems. ICIIECS, 4 (November 2014), 6-9.
Abstract
In this paper, it is attempted to analyze the power performances of few CMOS digital circuits such as full adder, multiplexer and SRAM cell with the inclusion and redesign of ultra low leakage (ULL) techniques. The basic principle behind this ULL is based on a pair of source-connected N-MOS and P- MOS transistors, automatically biasing the stand-by gate-to source voltage of N-MOSFET at negative and P-MOSFET at a positive voltage levels, thereby pushing the leakage current towards its physical limits. Virtual ground concept is also introduced to reduce the power dissipation further. The circuits are designed with DSCH schematic design tool using CMOS 90nm technology and simulations are performed by using Level3 model files. The final layout of all circuits is generated using microwind. From the obtained results, a significant amount of power reduction is noticed without other functional performances such as area and speed are getting affected.
References
- Denis Flandre, Olivier Bulteel, Geoffroy Gosset, Bertrand Rue and David Bol," Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal Microsystems"
- S. Adriaensen, V. Dessard, D. Flandre, «25 to 300°C ultra-low-power voltage reference compatible with standard SOI CMOS process», Electronics Letters, vol. 38, pp. 1103-1104, 2002.
- D. Levacq, C. Liber, V. Dessard, D. Flandre, " Composite ULP diode fabrication, modelling and applications in multi-Vth FD SOI CMOS technology " , Solid-State Electronics, vol. 48, pp. 1017-1025, 2004.
- D. Levacq, V. Dessard, D. Flandre, "Ultra-low power flip-flops for MTCMOS circuits", IEEE Int. Symposium on Circuits and Systems (ISCAS), pp. 4681-4684, May 2005.
- D. Levacq, V. Dessard, D. Flandre, "Low leakage SOI CMOS static memory cell with ultra-low power diode " , IEEE Journal Of Solid-State Circuits, vol. 42, pp. 689-702, March 2007.
- D. Bol, J. De Vos, R. Ambroise, D. Flandre, J. -D. Legat, «Building ultra-low-power high-temperature digital circuits in standard highperformance SOI technology», Solid-State Electronics, vol. 52, pp. 1939-1945, Dec. 2008.
- G. Gosset, B. Rue, D. Flandre, Very High Efficiency 13. 56MHz RFID Input Stage Voltage Multipliers Based on Ultra Low Power MOS diodes. IEEE Int. Conf. on RFID, April 16-17, 2008, Las Vegas, Nevada.
- D. Bol, J. De Vos and, D. Flandre, " Ultra-Low-Power High-Noise-Margin Logic with Undoped FD SOI Devices", IEEE Int. SOI Conf. , 2 p. , Oct. 2009.
- G. Gosset, D. Flandre, «A very high efficiency ultra-low- power 13. 56MHz voltage rectifier in 150nm SOI CMOS», IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) Singapore, Dec. 2009.
- Massoud Pedram, "Design Technologies for Low Power VLSI " Encyclopedia of Computer Science and Technology, 1995.
- O. Bulteel, R. Delamare, D. Flandre, «High-efficiency solar cell embedded in SOI substrate for ULP autonomous circuits», IEEE International SOI Conference, California/USA, 5-8 Oct. 2009.
Index Terms
Keywords