The upcoming trend in VLSI technology has led to the miniaturization of semiconductor devices which in turn is strongly dependent on the advancement in the CMOS technology. The present technology is below sub-100 nm in channel length which is the minimum dimension of single device. As CMOS technology dimensions are being intrusively scaled down to the fundamental limits such as reduction in carrier mobility due to impurity, increasing gate tunneling effect as the gate oxide thickness decreases, increasing p-n junction leakage current as the junction become more and more shallow, etc. . Established by the material characteristics, secondary effects begin to influence the performance of the device significantly and more accurate device models such as MOS device structures are needed to be developed. All these requirements have led to development of alternative technology which is the (SOI) Silicon-On-Insulator technology. This SOI is one such alternative technology which can offer the performance that is expected by the next generation Si technology. In my work, a Dual-Material Double Gate Fully-Depleted SOI MOSFET has been analyzed. The analytical model for the MOSFET's electrical parameters (such as electric field distribution, electron velocity distribution, sub-threshold swing, threshold voltage, device capacitance, drain-current, trans-conductance, drain-resistance, cut-off frequency and transit time) has been developed and the results are compared by numerical analysis using ATLAS. It has been seen that this structure provides for significant improvement in high frequency behavior of the device. And an effort has been taken to control the short-channel effects.

1. M. J. Kumar and A. Chaudhry, "Two-dimensional analytical modeling of fully depleted Dual-Material Gate (DMG) SOI MOSFET and evidence for diminished short-channel effects," IEEE Trans Electron Devices,vol. 15, pp. 569–574, Apr. 2004.
2. W. Long, H. Ou, J. -M. Kuo, and K. K. Chin, "Dual material gate(DMG) field effect transistor," IEEE Trans. Electron Devices, vol. 46,pp. 865–870, May 2005.
3. D. Disney, W. Chan, R. Lam, R. Blattner, S. Ma, W. Seng, J. -W. Chen, M. Cornell, and R. Williams, "60 V lateral trench MOSFET in 0. 35 ?m technology," in Proc. ISPSD, 2006,pp. 24–27.
4. Takayasu Sakurai, Akira Matsuzawa and TakakuniDouseki, "Fullt-Depleted SOICMOS Circuits and Technology for Ultralow-Power Applications", Springer, 2006.
5. X. Luo, Z. J. Li, B. Zhang, D. Fu, Z. Zhan, K. Chen, S. Hu, Z. Zhang, Z. Feng, and B. Yan, "Realization of high voltage (>700 V) in new SOI devices with a compound buried-layer," IEEE Electron Device Lett. , vol. 29, no. 12, pp. 1395–1397, Dec. 2009.
6. X. Luo, T. F. Lei, Y. Wang, H. Gao, J. Fang, M. Qiao, W. Zhang, H. Deng, B. Zhang, Z. Li, Z. Xiao, Z. Chen, and J. Xu, "A high-voltage LDMOS compatible with high voltage integrated circuits on p-type SOI layer," IEEE Electron Device Lett. , vol. 30, no. 10, pp. 1093–1095, Oct. 2010.
7. C. Sampedro-Matarin, F. J. Gamiz, A. Godoy, and F. Garcia-Ruiz, "Thmultivalley effective conduction band-edge method for Monte Carlo simulation of nanoscale structures," IEEE Trans. Electron Devices, vol. 53,no. 11, pp. 2703–2710, Nov. 2012.
8. C. Sampedro-Matarin, F. J. Gamiz, A. Godoy, and F. Garcia-Ruiz, "The multivalley effective conduction band-edge method for Monte Carlo simulation of nanoscale structures," IEEE Trans. Electron Devices, vol. 53,no. 11, pp. 2703–2710, Nov. 2006.
9. Takayasu Sakurai, Akira Matsuzawa and TakakuniDouseki, "Fully-Depleted SOICMOS Circuits and Technology for Ultralow-Power Applications", Springer, 2006.
10. http://www-device. eecs. berkeley. edu/bsim/

Dual Material Double Gate Atlas Device Simulator Soi