Dynamic comparators are used in high speed analog to digital converters. In this paper low voltage, low power dynamic comparators are designed in 130 nm technology and the analysis of the power consumption and delay will be presented. Based on the presented analysis, a new dynamic comparator is proposed. By using power gating technique and adding few transistors, the positive feedback during the regeneration is strengthened in the proposed comparator structure. Post layout simulation results in 0. 130µm CMOS technology confirm the analysis results. In the proposed comparator the power consumption is significantly reduced.

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Double-tail Comparator Dynamic Clocked Comparator High-speed Analog-to-digital Converters (adcs) Low-power Analog Design