CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Low Complexity Implementation Of LDPC Decoder using MIN-Sum Algorithm

Published on December 2013 by Geo Niju Shanth, Saru Priya
journal_cover_thumbnail

International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
Foundation of Computer Science USA
ICIIIOES - Number 1
December 2013
Authors: Geo Niju Shanth, Saru Priya
ea9f9e0e-2b44-4c40-94d5-f4af5e879f92

Geo Niju Shanth, Saru Priya . Low Complexity Implementation Of LDPC Decoder using MIN-Sum Algorithm. International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences. ICIIIOES, 1 (December 2013), 37-41.

@article{
author = { Geo Niju Shanth, Saru Priya },
title = { Low Complexity Implementation Of LDPC Decoder using MIN-Sum Algorithm },
journal = { International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences },
issue_date = { December 2013 },
volume = { ICIIIOES },
number = { 1 },
month = { December },
year = { 2013 },
issn = 0975-8887,
pages = { 37-41 },
numpages = 5,
url = { /proceedings/iciiioes/number1/14284-1367/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
%A Geo Niju Shanth
%A Saru Priya
%T Low Complexity Implementation Of LDPC Decoder using MIN-Sum Algorithm
%J International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
%@ 0975-8887
%V ICIIIOES
%N 1
%P 37-41
%D 2013
%I International Journal of Computer Applications
Abstract

This paper presents a resource efficient LDPC decoder architecture. The algorithm used for decoding LDPC is the min-sum algorithm. The decoder reduces the inter-connect complexity by restricting the extrinsic message length to 2 bits and also simplifies the check node operation. The algorithm is simulated and the results show that the performance is better than that of other algorithms. This algorithm can be incorporated into partially parallel hardware architecture to get significant savings in hardware resources when implemented in FPGA.

References
  1. R. Gallager, Low-density parity-check codes, IRE Transactions on Information Theory 8 (1) (1962) 21–28. .
  2. D. J. C. MacKay, Good error-correcting codes based on very sparse matrices, IEEE Transactions on Information Theory 45 (2) (1999) 399–431.
  3. Tetsuo Nozawa, LDPC Adopted for Use in Comms, Broadcasting, HDDs, Tech On, 2005. Tavel, P. 2007 Modeling and Simulation Design. AK Peters Ltd.
  4. G. L. L. Nicolas Fau, LDPC (Low Density Parity Check)— A Wireless PHY Layers EE Times Network, 2008
  5. A. Anastasopoulos, A comparison between the sum-product and the min-sum iterative detection algorithms based on density evolution, in: Proceedings of the IEEE Global Telecommunications Conference, San Antonio, TX, pp. 1021– 1025, 25–29 November 2001.
  6. R. Zarubica, R. Hinton, S. G. Wilson, E. K. Hall, Efficient quantization schemes for LDPC decoders, in: Proceedings of the 'IEEE Military Communications Conference, San Diego, CA, pp. 1–5, 16–19 November 2008.
  7. Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, An area efficient LDPC decoder using a reduced complexity min-sum algorithm. Integration, the VLSI journal, Volume 45, Issue 2, March 2012.
  8. J. G. Proakis, Digital Communications, Fifth ed, McGraw-Hill, New York, 2008.
  9. M. Fossorier. Quasi-cyclic low-density parity-check codes from circulant permutation matrices. IEEE Transaction Information Theory, 50(8):1788–1793, Aug. 2004.
  10. J. Zhao, F. Zarkeshvari, and A. H. BanihaShemi. On the implementation of Min-Sum Algorithm and its modifications for Decoding Low-Density Parity-Check Codes. IEEE Transactions on Communications, 53(4):549–554, April 2005.
  11. K. Shimizu, T. Ishikawa, N. Togawa, T. Ikenaga, S. Goto, Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm, in: Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 503–510, 2–5 October 2005.
Index Terms

Computer Science
Information Sciences

Keywords

Error Correction Coding Ldpc Code Iterative Decoding Vlsi Design