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Reseach Article

Efficient Implementation of Parallel Linear Phase FIR Filters using Polyphase Decomposition

Published on December 2013 by Jani Thivya. T, R. Latha
International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
Foundation of Computer Science USA
ICIIIOES - Number 6
December 2013
Authors: Jani Thivya. T, R. Latha
cd922973-0592-42a2-b516-91510d860927

Jani Thivya. T, R. Latha . Efficient Implementation of Parallel Linear Phase FIR Filters using Polyphase Decomposition. International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences. ICIIIOES, 6 (December 2013), 1-5.

@article{
author = { Jani Thivya. T, R. Latha },
title = { Efficient Implementation of Parallel Linear Phase FIR Filters using Polyphase Decomposition },
journal = { International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences },
issue_date = { December 2013 },
volume = { ICIIIOES },
number = { 6 },
month = { December },
year = { 2013 },
issn = 0975-8887,
pages = { 1-5 },
numpages = 5,
url = { /proceedings/iciiioes/number6/14317-1527/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
%A Jani Thivya. T
%A R. Latha
%T Efficient Implementation of Parallel Linear Phase FIR Filters using Polyphase Decomposition
%J International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
%@ 0975-8887
%V ICIIIOES
%N 6
%P 1-5
%D 2013
%I International Journal of Computer Applications
Abstract

This paper presents an efficient approach that greatly reduces the hardware consumption during the design of FIR filters. Linear phase FIR filters are designed by exploiting the nature of symmetric odd coefficients. The efficient usage of coefficients limits the number of multipliers while simultaneously increasing the number of adders, which does not influence the hardware cost to a greater extent. Parallel processing together with linear phasing is a powerful technique which can be used to increase the throughput of the FIR filter or reduce the power consumption of the FIR filter. Replacement of adders instead of multipliers is advantageous because adders weigh less in cost in terms of its silicon area and also the number of sub filter blocks remains fixed and does not increase along with the length of the FIR filter. By using the combination of fast FIR filtering and area reduction technique, a major reduction of multipliers is done.

References
  1. D. A. Parker and K. K. Parhi , " Low area-power parallel FIR digital filter implementations," J. VLSI Signal Process. Syst. ,vol. 17, no. 1, pp. 75-92, Sep. 1997.
  2. J. G. Chung and K. K. Parhi, "Frequency-spectrum based low-power parallel FIR filter design," EURASIP J. Appl. Signal Process. , vol. 2002, no. 9, pp. 444-453, Jan. 2002.
  3. K. K. Parhi, VLSI Digital Signal Processing Systems : Design & Implementation, Newyork : Wiley,1999.
  4. Z. -J. Mou and P. Duhamel, "Short-length FIR filters and their use in fast nonrecursive filtering," IEEE Trans. Signal Process. , vol. 39, no. 6, pp. 1322-1332, Jun. 1991.
  5. Y. C. Tsao and K. Choi, "Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 20, no. 2, pp. 366-371, Feb. 2010.
  6. J. I. Acha, "Computational structures for fast implementation of L-path and L-block digital filters," IEEE Trans. Circuits Syst. , vol. 36, no. 6, pp-805-812, Jun. 1989.
  7. C. Cheng and K. K. Parhi, "Hardware efficient fast parallel FIR filter structures based on iterated short convolution," IEEE. Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 8, pp. 1492-1500, Aug. 2004
  8. C. Cheng and K. K. Parhi. "Further complexity reduction of parallel FIR filters," in Proc. IEEE ISCAS, May 2005, vol. 2, pp. 1835-1838.
  9. C. Cheng and K. K. Parhi, "Low-cost parallel FIR Structures with 2-stage parallelism," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 280-290, Feb. 2007.
  10. I. –S. Lin and S. K. Mithra, " Overlapped block digital filtering," IEEE Trans. Circuits Syst. II,Analog Digit. Signal Process. , vol. 43, no. 8, pp-586-596, Aug. 1996.
Index Terms

Computer Science
Information Sciences

Keywords

Digital Signal Processing (dsp) - Fir Filter –linear Phase – Parallel Processing – Odd Coefficients.