In mathematics, multiplication is the most commonly used operation. This paper explores the design approach of a convolution encoder using vedic multiplier which leads to improve delay and faster speed. Here, the efficiency of Urdhva Triyagbhyam Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of partial products and eliminates unwanted multiplication steps. This algorithm follows a fast multiplication process and achieves a significantly less computational complexity over its conventional counterparts. The coding is in VHDL and synthesis is in Xilinx ISE simulator.

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Convolutional Encoder Multiplier Urdhava Tiryakbhyam Vedic Mathematics.