CFP last date
21 October 2024
Reseach Article

Convolutional Encoder Design using 16 Bit Vedic Multiplier on High Speed Revolution

Published on October 2014 by Shreyasi P. Bhat, and Ravindra D. Kadam, Prashant R. Indurkar
International Conference on Quality Up-gradation in Engineering, Science and Technology
Foundation of Computer Science USA
ICQUEST - Number 2
October 2014
Authors: Shreyasi P. Bhat, and Ravindra D. Kadam, Prashant R. Indurkar
6f807337-308f-42b7-8bc0-686c30e4c6ee

Shreyasi P. Bhat, and Ravindra D. Kadam, Prashant R. Indurkar . Convolutional Encoder Design using 16 Bit Vedic Multiplier on High Speed Revolution. International Conference on Quality Up-gradation in Engineering, Science and Technology. ICQUEST, 2 (October 2014), 12-15.

@article{
author = { Shreyasi P. Bhat, and Ravindra D. Kadam, Prashant R. Indurkar },
title = { Convolutional Encoder Design using 16 Bit Vedic Multiplier on High Speed Revolution },
journal = { International Conference on Quality Up-gradation in Engineering, Science and Technology },
issue_date = { October 2014 },
volume = { ICQUEST },
number = { 2 },
month = { October },
year = { 2014 },
issn = 0975-8887,
pages = { 12-15 },
numpages = 4,
url = { /proceedings/icquest/number2/18694-1542/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Quality Up-gradation in Engineering, Science and Technology
%A Shreyasi P. Bhat
%A and Ravindra D. Kadam
%A Prashant R. Indurkar
%T Convolutional Encoder Design using 16 Bit Vedic Multiplier on High Speed Revolution
%J International Conference on Quality Up-gradation in Engineering, Science and Technology
%@ 0975-8887
%V ICQUEST
%N 2
%P 12-15
%D 2014
%I International Journal of Computer Applications
Abstract

In mathematics, multiplication is the most commonly used operation. This paper explores the design approach of a convolution encoder using vedic multiplier which leads to improve delay and faster speed. Here, the efficiency of Urdhva Triyagbhyam Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of partial products and eliminates unwanted multiplication steps. This algorithm follows a fast multiplication process and achieves a significantly less computational complexity over its conventional counterparts. The coding is in VHDL and synthesis is in Xilinx ISE simulator.

References
  1. Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim, Yong Beom Cho, Multiplier design based on ancient Indian Vedic Mathematics, 978-1-4244-2599-0/08 2008 IEEE.
  2. Shamim Akhter, VHDL IMPLEMENTATION OF FAST NXN MULTIPLIER BASED ON VEDIC MATHEMATIC, 1-4244-1342-7/07 2007 IEEE.
  3. Vaijyanath Kunchigi, Linganagouda Kulkarni, Subhash Kulkarni, High Speed and Area Efficient Vedic Multiplier.
  4. Ms. G. S. Suganya, Ms. G. kavya, RTL Design and VLSI Implementation of an efficient Convolutional Encoder and Adaptive Viterbi Decoder, 978-1-4673-4866-9/13/2013 IEEE.
  5. V. Kavinilavu1, S. Salivahanan, V. S. Kanchana Bhaaskaran2, Samiappa Sakthikumaran, B. Brindha and C. Vinoth, Implementation of Convolutional Encoder and Viterbi Decoder using Verilog HDL, 978-1-4244-8679-3/11/2011 IEEE.
  6. Anuradha Kulkarni, Dnyaneshwar Mantri, Neeli R Prasad, Ramjee Prasad, Convolutional Encoder and Viterbi Decoder Using SOPC For Variable Constraint Length, 978-1-4673-4529-3/12/ 2012 IEEE.
  7. Sishir Kalita, Parismita Gogoi & Kandarpa Kumar Sarma, Convolutional Coding Using Booth Algorithm For Application in Wireless Communication, International Journal of Electronic Signals and Systems.
  8. Yin Sweet Wong, Wen Jian Ong, Jin Hui Chong, Chee Kyun Ng, Nor Kamariah Noordin, Implementation of Convolutional Encoder and Viterbi Decoder using VHDL, 978-1-4244-5187-6/09 2009 IEEE.
  9. Jayashree Taralabenchi, Kavana Hegde, Soumya Hegde, Siddalingesh S. Navalgund, Implementation of Binary Multiplication using Booth and Systolic Algorithm on FPGA using VHDL, International Conference & Workshop on Recent Trends in Technology, (TCET) 2012.
  10. A. J. Viterbi, "Error bounds for convolutional coding and an asymptotically optimum decoding algorithm", IEEE Tran. On Inform. Theory, Vol. 2, Pp. 260-269, Apr. 1967.
  11. Wong, Y. S. "Implementation of convolutional encoder and Viterbi decoder using VHDL" IEEE Tran. on Inform. Theory, Pp. 22-25, Nov. 2009.
  12. S. Vikrama Narasimha Reddy, Charan Kumar . K , Neelima Koppala, "Design of Convolutional Codes for varying Constraint Lengths", International Journal of Engineering Trends and Technology- Volume4Issue1- 2013
  13. Irfan Habib, Özgün Paker, Sergei Sawitzki, "Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation" IEEE Tran. on Very Large Scale Integration (VLSI) Systems, Vol. 18, Pp. 794-807, May 2010. 300.
  14. G. Ganesh Kumar, V. Charishma, "Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques", International Journal of Scientific and Research Publications, Volume 2, Issue 3, March 2012
  15. Ms. Shreyasi P. Bhat, Prof. Ravindra D. Kadam , Prof. Prashant R. Indurkar , "Review of high speed convolutional encoder design using ancient Indian Vedic Sutra", IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE), PP 41-45, (ICAET-2014)
Index Terms

Computer Science
Information Sciences

Keywords

Convolutional Encoder Multiplier Urdhava Tiryakbhyam Vedic Mathematics.