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Design and Implementation of HDLC Transmitter using VHDL

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IJCA Proceedings on International Conference on Quality Up-gradation in Engineering Science and Technology
© 2017 by IJCA Journal
ICQUEST 2016 - Number 2
Year of Publication: 2017
Authors:
Rupal P. Bende
A. P. Bagade
S. R. Salwe

Rupal P Bende, A P Bagade and S R Salwe. Article: Design and Implementation of HDLC Transmitter using VHDL. IJCA Proceedings on International Conference on Quality Up-gradation in Engineering Science and Technology ICQUEST 2016(2):5-7, August 2017. Full text available. BibTeX

@article{key:article,
	author = {Rupal P. Bende and A. P. Bagade and S. R. Salwe},
	title = {Article: Design and Implementation of HDLC Transmitter using VHDL},
	journal = {IJCA Proceedings on International Conference on Quality Up-gradation in Engineering Science and Technology},
	year = {2017},
	volume = {ICQUEST 2016},
	number = {2},
	pages = {5-7},
	month = {August},
	note = {Full text available}
}

Abstract

Data communication over the network is efficiently carried out with the help of protocol. Protocol is set of rules that define the format of frame, packet or message that are exchanged between devices. HDLC i. e. High level data link control protocol is one of the protocol defined by International Organization for Standardization (ISO) for data link layer of OSI reference model. HDLC is bit oriented protocol and widely used in the network. It is used to send the data in proper frame format. This paper discusses the design of HDLC transmitter coded in VHDL and its simulation in Modelsim software.

References

  • Rupal P. Bende,. A. P. Bagade, Prof. S. R. Salwe," Review on Design of HDLC Protocol using HDL", International Journal of Innovative Research in Electrical, Electronics, Instrumentation and control engineering, Vol. 4, Issue 2, February 2016.
  • Syed Manzoor Qasim and Shuja A. Abbasi ," FPGA Implementationof a Single-Channel HDLC Layer-2 Protocol Transmitter using VHDL", International Conference on Electrical, Electronics and System Engineering, 2003.
  • S. Hamed Javadi and Ali Peiravi,"Design and Implementation of a High Bit Rate HDLC Transceiver Based on a Modified MT8952 Controller", Australian Journal of Basic and Applied Sciences,2009.
  • K. Sakthidasan, Mohammed Mahommed,"Design of HDLC Controller Using VHDL", International Journal of Scientific & Engineering Research Volume 2, Issue 3, March-2011.
  • Harpreet Singh, Navneet Kaur, Vinay Chopra and Dr. Amardeep Singh," Optimization of multi - channel HDLC protocol transceiver using Verilog", International Journal of Computer Science Issues, Vol. 9, Issue 2, No 2, March 2012.
  • Armaan Hasan Nagpurwala,Sundaresan C, Chaitanya CVS, "Implementation of HDLC Controller Design using Verilog HDL ", International Conference on Electrical, Electronics and System Engineering,2013.
  • Gaurav Chandil, Priyanka Mishra,"Design and Implementation of HDLC Controller by Using Crc-16", International Journal of Modern Engineering Research (IJMER) Jan. -Feb. 2013.
  • Jai Karan Singh1, Mukesh Tiwari, Mohd Firoz Warsi,"Implementation of HDLC Protocol Based DDR-RAM Radar Processing System", International Journal of VLSI and Embedded Systems-IJVES -May - June 2013.
  • Shubham Fadnavis,"An HVD Based Error Detection and Correction Code in HDLC Protocol Used for Communication", International Journal of Advanced Research in Computer and Communication Engineering, Vol. 2, Issue 6, June 2013.
  • Shashank Rampelly, Santhosh Rao Seri, Gnaneshwara Chary, Krishanm Raju, "Data Communication Using HDLC Protocol", International Journal of Innovative Research in Electrical, Electronics, Instrumentation and control engineering ,Vol. 2, Issue 5, May 2014.
  • Gao, Zhen-bin and Jian-Fei Liu,"FPGA implementation of a multi-channel HDLC protocol transceiver", In Proceedings of the 2005 International Conference on Communications, Circuits and Systems,2: 1300-1302,2005.
  • Lu, Y. , Z. Wang, L. Qiao and B. Huanq, "Design and implementation of multi-channel high speed HDLC data processor," IEEE International Conference on Communications, Circuits and Systems, and West Sino Expositions, 2: 1471-1475,2002.
  • Jun Wang; Wenhao Zhang; Yuxi Zhang; Wei Wu; Weiguang Chang; Sch. of Electron. & Inf. Eng. , Beihang Univ. (BUAA), Beijing, China "Design and implementation of HDLC procedure based on FPGA" , Anti-counter feiting, Security, and Identification in Communication, ASID, 3rd International Conference, 20-22 Aug. 2009.
  • Wang Lie, Yi Mingvol, "Design of HDLC Controller based on XILINX FPGA ", International Conference on Electrical, Electronics and System Engineering IEEE, 2011.