Call for Paper - August 2022 Edition
IJCA solicits original research papers for the August 2022 Edition. Last date of manuscript submission is July 20, 2022. Read More

Design of High Speed 32-bit Adder and Sub-tractor Module

Print
PDF
IJCA Proceedings on International Conference on Quality Up-gradation in Engineering Science and Technology
© 2017 by IJCA Journal
ICQUEST 2016 - Number 2
Year of Publication: 2017
Authors:
Ashwini B. Kewate
P. R. Indurkar
A . W. Hinganikar

Ashwini B Kewate, P R Indurkar and A w Hinganikar. Article: Design of High Speed 32-bit Adder and Sub-tractor Module. IJCA Proceedings on International Conference on Quality Up-gradation in Engineering Science and Technology ICQUEST 2016(2):8-11, August 2017. Full text available. BibTeX

@article{key:article,
	author = {Ashwini B. Kewate and P. R. Indurkar and A .w. Hinganikar},
	title = {Article: Design of High Speed 32-bit Adder and Sub-tractor Module},
	journal = {IJCA Proceedings on International Conference on Quality Up-gradation in Engineering Science and Technology},
	year = {2017},
	volume = {ICQUEST 2016},
	number = {2},
	pages = {8-11},
	month = {August},
	note = {Full text available}
}

Abstract

This paper describes a improved version of design of 32 bit adder module and 32 bit of sub- tractor module by using VHDL. Multiplier is the main component in digital signal processing. For designing floating point multiplier, adder and sub-tractor modules are essentially required. The floating point complex multiplication is one of the basic functions used in digital signal processing application, microprocessors and FIR filters. Floating point format is a standard format used almost in all processing elements. The Objective of this paper is to implement the 32 bit binary floating point adder and sub-tractor with minimum delay. The modules required for the design, are coded in VHDL as it is very useful tool. Simulation and functional analysis is done in Xilinx ISE14. 5. It is observed that the delay required for this design is improved as compared to earlier work. .

References

  • Ali Malik, Seok-Bum Ko, "A Study On The Floating Point Adders In FPGA ",1- 4244- 0038- 4-2006 IEEE CCECE/CCGEI, Ottawa, May 2006.
  • SanghoYun ," A Low Complexity Floating-Point Complex Multiplier with a Three-term Dot-Product Unit", 978-1-4799-5274-8/14/$31. 00 ©2014 IEEE.
  • Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat, "High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics", Proceeding of the 2011 IEEE Students' Technology Symposium 14-16 January, 2011, IIT Kharagpur, 978-1-4244-8943-5/11/$26. 00 ©2011 IEEE.
  • Laxman P. Thakare, A. Y. Deshmukh and Gopichand D. Khandale, "VHDL Implementation of Complex Number Multiplier Using Vedic Mathematics", Proceedings of International Conference on Soft Computing Techniques and Engineering Application, Advances in Intelligent Systems and Computing 250, DOI: 10. 1007/978-81-322-1695-7_46, Springer India 2014.
  • Ankush Nikam, Swati Salunke, Sweta Bhurse,"Design and Implementation of 32bit Complex Multiplier using Vedic Algorithm", International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 IJERTV4IS030821,Vol. 4 Issue 03, March-2015.
  • Swaroop a. Gandewar, mamta sarde," Design of vedic multiplier for complex numbers for enhanced computation using vhdl", Proceedings of 4th SARC International Conference, 30th March-2014, Nagpur, India.
  • Mr. Swaroop A. Gandewar, Mamta Sarde2,"Design of 8 Bit Vedic Multiplier for Real & Complex Numbers Using VHDL" International Journal of Engineering Research and Applications (IJERA April 2014).
  • Rajashri Bhongade S. G. Mungale Karuna Bogavar,"Performance Evaluation of High Speed Complex Multiplier Using Vedic Mathematics", International Journal of Innovative Research in Advanced Engineering (IJIRAE) Volume 1 Issue 1 (April 2014).
  • Irine Padma B. T, Suchitra. K, "Pipelined Floating Point Multiplier Based On Vedic Multiplication Technique", International Journal of Innovative Research in Science, Engineering and Technology Certified Organization Volume 3, July 2014.
  • S Venkateswara Reddy, "Design and implementation of 32 bit Multipier using vedic mathamatics", International Journal of Advanced Research in Electrical,Electronics and Instrumentation Engineering Vol. 2, Issue 8, August 2013.
  • Pankaj Singh Bhavin Kakani,"Performance Comparison of Floating Point Multipliers by using Different Multiplication Algorithms", IPASJ International Journal of Electronics & Communication (IIJEC)Volume 3, Issue 1, January 2015.