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Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL

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IJCA Proceedings on International Conference on Quality Up-gradation in Engineering Science and Technology
© 2017 by IJCA Journal
ICQUEST 2016 - Number 2
Year of Publication: 2017
Authors:
Bhagyashree. V. Dagamwar
R. N. Mandavgane
D. M. Khatri

Bhagyashree. V Dagamwar, R N Mandavgane and D M Khatri. Article: Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL. IJCA Proceedings on International Conference on Quality Up-gradation in Engineering Science and Technology ICQUEST 2016(2):12-16, August 2017. Full text available. BibTeX

@article{key:article,
	author = {Bhagyashree. V. Dagamwar and R. N. Mandavgane and D. M. Khatri},
	title = {Article: Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL},
	journal = {IJCA Proceedings on International Conference on Quality Up-gradation in Engineering Science and Technology},
	year = {2017},
	volume = {ICQUEST 2016},
	number = {2},
	pages = {12-16},
	month = {August},
	note = {Full text available}
}

Abstract

In general, multiplication plays an vital role in the development of processors, DSP applications, image processing etc. So, designing of high speed multiplier is a neccesary choice. In this research, design of 4, 8 and 16-bit multiplier based on vedic mathematics has been presented. These multipliers further will be used in the design of convolutional encoder. Here, Urdhava Tiryakbhyam sutra is used for multiplication. It eliminates unwanted multiplication steps and follows a fast multiplication process and achieves a significantly less computation complexity over its conventional counterparts. All the modules are coded in VHDL and simulation done in Xilinx ISE 14. 5i.

References

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