This paper proposes a watermarking scheme for intellectual property (IP) identification based on testing method in soc design. The core concept is embedding the watermarking generating circuit (WGC) and test circuit (TC) in to the soft IP core at the behavioural design level. Therefore this scheme can successfully survive synthesis, placement and routing and can identify the IP core at various design levels. The IP core does not change after manufactured the chip also . This method adopts current main system-on-chip (SOC). The identity of the IP is proven during the general test process without implementing any extra extraction flow. After the chip has been manufactured and packaged, it is still easy to detect the identification of the IP provider without the need of microphotograph. This approaches entail low hardware overhead, tracking costs, The proposed method solves the IP-identification problem.

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intellectual-property (IP) system-on-a-chip (SOC) very large scale integration (VLSI) design watermarking generating circuit (WGC) test circuit (TC)