In this paper,we propose a new technique for Multiplication based on multiplexers which will consume less area and power.The simulation has been done using Verilog HDL and synthesised by using Xilinx at a frequency of 5GHz.

1. On Built-In Self-Test for Multipliers by Mary D.Pulukuri, George J. Starr, and Charles E. Stroud, 2010 IEEE.
2. High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications by Jiun-Ping Wang, Shiann-Rong Kuang, Member, IEEE, and Shish-Chang Liang, 2009 IEEE
3. Low-Power Multiplier Optimized by Partial-Product Summation and Adder Cells by Meng-Lin Hsia and Oscal T.-C.Chen, 2009 IEEE.
4. A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm by Young- Ho Seo, Member IEEE, 2009 IEEE.
5. High-Performance VLSI Adders Bart R. Zeydel, Member, IEEE, Dursun Baran, Student Member, IEEE, and Vojin G. Oklobdzija, Fellow, IEEE, 2010 IEEE
6. Improving FPGA Performance for Carry-Save Arithmetic by Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, and Paolo Ienne, 2010 IEEE

Modified Fast Multiplier Verilog HDL