Many digital signals processing operation requires several multiplication and for the same we need very fast multiplier for a wide range of requirements for hardware and speed. This paper presents a FFT using for fast and area efficient digital multiplier based on Vedic algorithm. Digital multipliers are the core components of all the digital signal processors (DSPs) and the speed of the DSP is largely determined by the speed of its multipliers. Fast Fourier Transform (FFT) plays an important role in many signal and image processing, data analyzing for vibration sensors, frequency measurement of earthquakes and telecommunication systems such as WiMax technology which presents both wide bandwidth and wireless solutions.

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Urdhva Triyakbhyam VHDL FFT