CFP last date
22 April 2024
Reseach Article

High Speed Power Efficient Asynchronous Adders

Published on None 2011 by Harish Boddapati, Akshay Naregalkar, Raju BL Dr
journal_cover_thumbnail
International Conference and Workshop on Emerging Trends in Technology
Foundation of Computer Science USA
ICWET - Number 10
None 2011
Authors: Harish Boddapati, Akshay Naregalkar, Raju BL Dr
fcf779fa-fccc-4c50-baa8-b39c663627a7

Harish Boddapati, Akshay Naregalkar, Raju BL Dr . High Speed Power Efficient Asynchronous Adders. International Conference and Workshop on Emerging Trends in Technology. ICWET, 10 (None 2011), 27-32.

@article{
author = { Harish Boddapati, Akshay Naregalkar, Raju BL Dr },
title = { High Speed Power Efficient Asynchronous Adders },
journal = { International Conference and Workshop on Emerging Trends in Technology },
issue_date = { None 2011 },
volume = { ICWET },
number = { 10 },
month = { None },
year = { 2011 },
issn = 0975-8887,
pages = { 27-32 },
numpages = 6,
url = { /proceedings/icwet/number10/2139-emdc224/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference and Workshop on Emerging Trends in Technology
%A Harish Boddapati
%A Akshay Naregalkar
%A Raju BL Dr
%T High Speed Power Efficient Asynchronous Adders
%J International Conference and Workshop on Emerging Trends in Technology
%@ 0975-8887
%V ICWET
%N 10
%P 27-32
%D 2011
%I International Journal of Computer Applications
Abstract

Adders are representative of signal processing architectures. In this paper three low power Asynchronous Full Adder circuits are proposed .Asynchronous circuits make it suitable for low power operation of the circuits. Asynchronous circuits stops computing when there is no change in the input there by eliminating the need for extra complexity of clock gating. Low power and low energy techniques such as minimizing the number of transistors, voltage scaling are used. The implication of voltage scaling is a wide range of variation in the delay. The reduction in power also minimizes the efforts for the heat dissipation and cooling expenses. The reduction in power also minimizes the efforts for the heat dissipation and cooling expenses. Asynchronous Adder circuits dissipate less power in applications where performance is non-limiting. Asynchronous adders can be implemented using static or dynamic circuits. Asynchronous dynamic adder circuits employ a single rail or dual rail logic or a combined logic. The Circuits are implemented using cadence 90nm Technology and simulated using Spectre simulator. The delay achieved is 36ps, 39.6ps, 35.9ps as compared to 239ps for PTL Adder when 1.2v supply voltage is considered the average power dissipated is 146nw,153.6nw,150.9nw and the power delay product (PDP) obtained is 5.25e-18, 6.09e-18,5.43e-18 as compared to PTL adder which is 46.8uw and 5.4e-15. There is a considerable amount of reduction in the Average Power dissipated, Delay and PDP for all the three proposed adders compared to PTL Adder when the supply voltages of 1.5v, 1v, and 0.7v are used.

References
  1. A.J. Martin, “Remarks on low-power advantages of asynchronous circuits,” Europe. Solid-State Circuits Conf. (ESSCIRC), 1998.
  2. A.J. Martin, M. Nyström et al., “The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller,” IEEE Int. Symp. Async. Systems and Circuits, May 2003.
  3. A.J. Martin, “Remarks on low-power advantages of asynchronous circuits,” Europ. Solid-State Circuits Conf., 1998
  4. D. Johnson, V. Akella, “Design and analysis of Asynchronous adders”, IEE Proc. on Com. & Dig.Tech., v145, pp 1-8, 1998.
  5. D. Radhakrishnan, "Low-Voltage Low-Power CMOS Full Adder", IEE Proceedings on Circuits Devices and Systems, Vol. 148, No. 1, pp. 19-24 February 2001.
  6. J. Sparso and S. Furber, Principles of Asynchronous Circuit Design: ASystems Perspective: Kluwer Academic Publishers, 2001.
  7. L.E.M. Brackenbury P.A. Riocreux, M. J. G. Lewis “Power reduction in self-timed circuits using early-open latch controllers,” Electronics Letters, 36(2):115-116, 2000.
  8. Mohamed A. Elgamel, Sumeer Goel, and Magdy A. Bayoumi, “Noise Tolerant Low Voltage XOR-XNOR for Fast Arithmetic,” 2003 Great Lakes Symposium on VLSI (GLSVLSI2003), April 28-29, 2003, Washington D.C
  9. S.M. Nowick, K.Y. Yun, P.A. Beerel, A.E. Dooply. “Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders,'' IEEE Async-97 Symposium,1997.
Index Terms

Computer Science
Information Sciences

Keywords

Asynchronous low power delay Full Adder Pass Transistor Dynamic static XOR gate