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Low Power error Detector Design by using Low Power Flip Flops Logic

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IJCA Proceedings on International Conference and Workshop on Emerging Trends in Technology 2014
© 2013 by IJCA Journal
ICWET2014 - Number 2
Year of Publication: 2013
Authors:
Dibyalekha Chaini
Priyanka Malgi
Snehal Lopes

Dibyalekha Chaini, Priyanka Malgi and Snehal Lopes. Article: Low Power error Detector Design by using Low Power Flip Flops Logic. IJCA Proceedings on International Conference and Workshop on Emerging Trends in Technology 2014 ICWET 2014(2):25-29, May 2013. Full text available. BibTeX

@article{key:article,
	author = {Dibyalekha Chaini and Priyanka Malgi and Snehal Lopes},
	title = {Article: Low Power error Detector Design by using Low Power Flip Flops Logic},
	journal = {IJCA Proceedings on International Conference and Workshop on Emerging Trends in Technology 2014},
	year = {2013},
	volume = {ICWET 2014},
	number = {2},
	pages = {25-29},
	month = {May},
	note = {Full text available}
}

Abstract

Low-power design is becoming a crucial design objective for the chip design engineer due to the growing demand on portable application and the increasing difficulties in cooling and heat removal. In the integrated circuits power consumption is one of the challenges like area and speed . In this paper a novel technique is proposed to design an error detector for the lower power consumption. Here the work has done by using two low power flip flops (1)have considered SVL5T TSPC FF method and(2) low power DFF . In the proposed system reduction of power is about 50 % - 70%. Some of the low power flip flop is also used in multimedia and phase detector application.

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