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UART Designing for Four Different Baud Rate for Cyclone III Family

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IJCA Proceedings on International Conference and Workshop on Emerging Trends in Technology 2014
© 2013 by IJCA Journal
ICWET2014 - Number 2
Year of Publication: 2013
Authors:
Sunita Satyaram Yadav
Asha Durafe
Pratik Kanani

Sunita Satyaram Yadav, Asha Durafe and Pratik Kanani. Article: UART Designing for Four Different Baud Rate for Cyclone III Family. IJCA Proceedings on International Conference and Workshop on Emerging Trends in Technology 2014 ICWET 2014(2):30-33, May 2013. Full text available. BibTeX

@article{key:article,
	author = {Sunita Satyaram Yadav and Asha Durafe and Pratik Kanani},
	title = {Article: UART Designing for Four Different Baud Rate for Cyclone III Family},
	journal = {IJCA Proceedings on International Conference and Workshop on Emerging Trends in Technology 2014},
	year = {2013},
	volume = {ICWET 2014},
	number = {2},
	pages = {30-33},
	month = {May},
	note = {Full text available}
}

Abstract

UART (Universal Asynchronous Receiver Transmitter) is used for short-distance, low speed, low-cost data exchange between computer and peripheral. They provide a means to send data with a minimum of wires. The data is sent bit-serially, and no clock signal is sent along with it. The fact that a clock is not transmitted with the data complicates the design of a UART. The two systems (sender and receiver) have separate, unsynchronized, clock signals. The programmable logic devices can be used for such application by developing core for UART. By using hardware descriptive language UART simulation can be tested before it can be loaded on programmable device. In this project we present UART which includes three modules which are the baud rate generator, receiver and transmitter.

References

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