The week's pick
Reseach Article
Performance Analysis of Graded Channel Double-Gate MOSFET in Nano-Regime using TCAD Simulation
| National Conference on Latest Initiatives and Innovations in Communication and Electronics |
| Foundation of Computer Science USA |
| IICE2016 - Number 1 |
| February 2017 |
| Authors: Aakanksha Lakhanpal, Shashi B. Rana, Ashwani K. Rana |
| 458f1ac6-0638-4008-8f20-772393b52538 |
Aakanksha Lakhanpal, Shashi B. Rana, Ashwani K. Rana . Performance Analysis of Graded Channel Double-Gate MOSFET in Nano-Regime using TCAD Simulation. National Conference on Latest Initiatives and Innovations in Communication and Electronics. IICE2016, 1 (February 2017), 1-4.
Abstract
Double -gate (DG) MOSFET has emerged as one of the most promising architecture for scaling CMOS devices down to nanometer size as compared to the planar single-gate MOSFETs. In this work, the impact of channel engineering on double gate MOSFET has been investigated. Further, the comparison of double-gate MOSFETs with the graded channel double-gate MOSFETs has been done in terms of performance parameters such as I-V characteristics, electric field, electron current density, space charge density using TCAD Simulator.
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