SRAM is the most crucial part of memory designs and are imperative in many simple or compound applications that implicate system on chip (SoCs). Power dissipation and stability has now become the most essential area of concern in sub-micron SRAM cell design with continuous technology scaling according to Moore's law. At latest, retrenchment of channel length MOSFET is directly proportional to the new technologies generating step by step with new innovative tools. With an improvement in technology there is a sudden retrenchment of channel length of MOSFET. Moreover, in this network of stability SRAM has become very essential and major area to research in. Static noise margin generate its crucial role in the stability of SRAM. This paper introduce to the basic 6T SRAM cell. The outperforms of this SRAM cell in elaboration with transient response and static noise margin is described with the counter fit results using the EDA tool Custom Designer at 90nm CMOS Technology.

1. E. Seevinck et al. , "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE J. Solid-State Circuits, vol. SC-22, no. 5 pp. 748-754, Oct. 1987.
2. E. Grossar "Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies", IEEE J. Solid-State Circuits,vol. 41,no. 11 ,pp. 2577-2588,Nov. 2006.
3. S. Birla et a. l. "Static Noise Margin Analysis of Various SRAM Topologies"IACSIT,pp. 304-309,vol. 3,No. 3,june 2011.
4. S. Nakata et al. ,"Increasing Static Noise Margin of Single-bit-line SRAM Lowering Bit-line Voltage during Reading". IEEE 54th International Midwest Symposium on Circuits and Systems 2011. pp. 1-4,7 Aug,2011.
5. PM Vansi Kiran et al. ,"Design and Analysis of Different types SRAM Cell Topologies" ICECS. pp. 167-173,26-27Feb,2015.
6. Paridhi Athe et al. . ,"A Comparative Study of 6T,8T and 9T Decanano SRAm Cell" ISIEA. pp. 889-894,4oct,2009.
7. M. Alioto, "Understanding DC behavior of sub-threshold CMOS logic through closed-form analysis," IEEE Transactions on Circuits and Systems I. vol. 57, no. 7, pp. 1597-1607, 2010.
8. S. Tavva et al. "Variation Tolerant 9T SRAM Cell Design" GLSVLSI'10,pp. 55-60,may 16, 2010.
9. Spector, A. Z. 1989. Achieving application requirements. In Distributed Systems, S. Mullender
10. 1 Hooman Farkhania, Ali Peiravia and Farshad Moradib, " A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology" Proc. Of Microelectronics journal, pp. 1556-1565, 2014.
11. M. kavitha et. al. , "Low power multimodal switch for leakage reduction and stability improvement in SRAM cell", Arabian journal for science and engineering,vol,41,no. 8,p. p 2945-2955,12Feb,2016.
12. Wang, J. ; Nalam, S. : Analyzing static and dynamic write margin for nanometer SRAMs. In: Proceedings of the ACM/IEEE International Symposium on LPED, pp. 129–134 (2008).
13. Expanding margins for writing," in Proc. [SSCC Dig. , pp. 480-481, Feb. 2005.
14. R. Heald et al. , "Variability in sub-100 nm SRAM designs," in Proc. IEEE/ACM ICCAD, Nov. 2004, pp. 347–352.

Static Random Access Memory (sram) Cmos Static Noise Margin (snm) Read Noise Margin Write Noise Margin Wordline Bitline.