CFP last date
20 June 2024
Reseach Article

Power Optimal Design of SRAM in 90 nm

Published on April 2012 by Ravi Goel, Rajeevan Chandel, Dhirendra Kumar
International Conference on Recent Advances and Future Trends in Information Technology (iRAFIT 2012)
Foundation of Computer Science USA
IRAFIT - Number 5
April 2012
Authors: Ravi Goel, Rajeevan Chandel, Dhirendra Kumar
0b1effbf-4ac1-4dcd-a10b-93955c61ae1e

Ravi Goel, Rajeevan Chandel, Dhirendra Kumar . Power Optimal Design of SRAM in 90 nm. International Conference on Recent Advances and Future Trends in Information Technology (iRAFIT 2012). IRAFIT, 5 (April 2012), 33-38.

@article{
author = { Ravi Goel, Rajeevan Chandel, Dhirendra Kumar },
title = { Power Optimal Design of SRAM in 90 nm },
journal = { International Conference on Recent Advances and Future Trends in Information Technology (iRAFIT 2012) },
issue_date = { April 2012 },
volume = { IRAFIT },
number = { 5 },
month = { April },
year = { 2012 },
issn = 0975-8887,
pages = { 33-38 },
numpages = 6,
url = { /proceedings/irafit/number5/5884-1040/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Recent Advances and Future Trends in Information Technology (iRAFIT 2012)
%A Ravi Goel
%A Rajeevan Chandel
%A Dhirendra Kumar
%T Power Optimal Design of SRAM in 90 nm
%J International Conference on Recent Advances and Future Trends in Information Technology (iRAFIT 2012)
%@ 0975-8887
%V IRAFIT
%N 5
%P 33-38
%D 2012
%I International Journal of Computer Applications
Abstract

Low threshold voltage and ultra thin oxide become essential in power optimal VLSI circuit design. This paper analyzes the effect of dual thickness and dual threshold on static random access memory (SRAM) leakage power. The different hybrid cell configurations are analyzed for power optimal design of SRAM in 90nm technology node. Cell ratio of SRAM is an essential parameter for area centric SRAM design. It also decides the non destructive read operation of SRAM cell. Variation of cell ratio has also been analyzed. The effect of voltage-scaling is also analyzed for SRAM cells. It is found that voltage-scaling reduces the energy consumption but at the cost of read and write delay in SRAM cells.

References
  1. Seevinck, E., List, F. J., and Lohstroh, J. 1987. Static-Noise Margin Analysis of MOS SRAM Cells. IEEE J. Solid-State Circuits, vol. sc-22, no. 5, Oct. 1987, pp. 748-754.
  2. Wang, D. P., Liao, H. J., Yamauchi, H., Chen, Y. H., Lin, Y. L., Lin, S. H., Liu, D. C., Chang, H. C., and Hwang, W. 2007. A 45 nm dual-port SRAM with write and read capability enhancement at low voltage. In Proceeding IEEE International SOC Conference. pp. 211-214.
  3. Taur, Y., Chandrakasan, A., Bowhill, W. J., and Fox, F. 2001. CMOS scaling and issues in sub-0.25 ?m systems. In Proceeding Design of High-Performance Microprocessor Circuits. pp. 27–45.
  4. Sirisantana, N., Wei, L., and Roy, K. 2000. High performance low power CMOS circuits using multiple channel length and multiple oxide thickness. In Proceeding International Conference on Computer Design. pp. 227-232.
  5. Zhang, K., et al. 2005.SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. IEEE J. Solid-State Circuits, vol. 40, no. 4, Apr. 2005, pp. 895-901.
  6. Kim, C. and Roy, K. 2002. Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessor. In Proceeding International Symposium Low Power Electronics and Design..
  7. Agarwal, A. and Roy, K. 2003. A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. In Proceeding International Symposium Low Power Electronics and Design.
  8. Azizi, N., Najm, F., and Moshovos A. 2003. Low-leakage asymmetric-cell SRAM. IEEE Trans. on Very Large Scale Integration Systems, vol. 11, no. 4, 2003, pp. 701-715.
  9. Kim, C. H., Kim, J., Mukhopadhyay, S., and Roy, K. 2005. A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. on Very Large Scale Integration Systems, vol. 13, no. 3, 2005, pp. 349- 357.
  10. Natarajan, S., Romanovsky, S., and Achyulhan, A. 2004. Deep submicron embedded SRAM design issues. In Proceeding 7th International Conference. on Solid State and Integrated circuit technology.
  11. Chuang, C. T., Mukhopadhyay, S., Kim, J. J., Kim, K., and Rao, R. 2007. High-Performance SRAM in Nanoscale CMOS: Design Challenges and Technique. In Proceeding IEEE International Workshop on Memory Technology, Design and Testing.
  12. Amelifard, B., Fallah, and F., Pedram, M. 2006. Reducing the Sub-threshold and Gate Tunneling Leakage of SRAM Cells using Dual-Vth and Dual TOX Assignment. In Proceeding of Design, Automation and Test Europe.
  13. PTM Models for MOSFETs, 2011. Online: http://ptm.asu. edu/.
  14. EDA Tool used, 2011. Online: http://www.tanner.com
  15. Pavlov, A., Sachdev, M., and Agrawal, V. 2008. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies. Springer, pp.13-80.
  16. Kang, S. M. and Leblebici, Y. 2003. CMOS Digital Integrated Circuits. MGH. pp. 417-435.
  17. Zhang, L. J., Wu, C., Ma, Y. Q., Zheng, J., and Mao, L. F. 2011. Leakage Power Reduction Technique of SRAM Cells. IETE Technical Review, pp. 135-144.
Index Terms

Computer Science
Information Sciences

Keywords

Cell Ratio Read Current Write Delay Pdp Voltage Scaling