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Reseach Article

Low Power High Speed 64 Bit SRAM Architecture using SCCMOS and Drowsy Cache Concept

Published on October 2014 by Geeta Pattnaik, Srinibasa Padhy
International Conference on Microelectronics, Circuits and Systems
Foundation of Computer Science USA
MICRO - Number 2
October 2014
Authors: Geeta Pattnaik, Srinibasa Padhy
39568dd2-6db9-445d-96d5-8101edc3c4de

Geeta Pattnaik, Srinibasa Padhy . Low Power High Speed 64 Bit SRAM Architecture using SCCMOS and Drowsy Cache Concept. International Conference on Microelectronics, Circuits and Systems. MICRO, 2 (October 2014), 17-22.

@article{
author = { Geeta Pattnaik, Srinibasa Padhy },
title = { Low Power High Speed 64 Bit SRAM Architecture using SCCMOS and Drowsy Cache Concept },
journal = { International Conference on Microelectronics, Circuits and Systems },
issue_date = { October 2014 },
volume = { MICRO },
number = { 2 },
month = { October },
year = { 2014 },
issn = 0975-8887,
pages = { 17-22 },
numpages = 6,
url = { /proceedings/micro/number2/18317-1814/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Microelectronics, Circuits and Systems
%A Geeta Pattnaik
%A Srinibasa Padhy
%T Low Power High Speed 64 Bit SRAM Architecture using SCCMOS and Drowsy Cache Concept
%J International Conference on Microelectronics, Circuits and Systems
%@ 0975-8887
%V MICRO
%N 2
%P 17-22
%D 2014
%I International Journal of Computer Applications
Abstract

With the development of technology with each passing days, the demand for low power, high speed, high density memory for portable devices is increasing proportionally. The power consumption and battery life has become the major concerns for VLSI industry. But as the technology scales down it gives rise to an unwanted parameter i. e. , the leakage power which according to International technology roadmap of semiconductors (ITRS) will dominate the majority part of the total power consumption . In this paper a complete 64 bits SRAM array is designed using the leakage power reduction techniques . 2 techniques are being combined which are sleep stack with keeper and other is the drowsy cache including the SCCMOS concept . The array is designed and simulated using cadence gpdk 180nm technology . The results show that the total power consumption has reduced by nearly 40% for 1 bit SRAM along with its peripherals

References
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Index Terms

Computer Science
Information Sciences

Keywords

Sleep Stack With Keeper Drowsy Cache Sccmos Data Retention Voltage Low Power Sram