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Reseach Article

Design of Optimized Wallace Tree Multiplier in Cadence

Published on October 2014 by Anindita Dash, Swetapadma Dash, S.k.mandal
International Conference on Microelectronics, Circuits and Systems
Foundation of Computer Science USA
MICRO - Number 2
October 2014
Authors: Anindita Dash, Swetapadma Dash, S.k.mandal
b45dfd9d-2ec5-48c5-9165-17b395987e4e

Anindita Dash, Swetapadma Dash, S.k.mandal . Design of Optimized Wallace Tree Multiplier in Cadence. International Conference on Microelectronics, Circuits and Systems. MICRO, 2 (October 2014), 33-38.

@article{
author = { Anindita Dash, Swetapadma Dash, S.k.mandal },
title = { Design of Optimized Wallace Tree Multiplier in Cadence },
journal = { International Conference on Microelectronics, Circuits and Systems },
issue_date = { October 2014 },
volume = { MICRO },
number = { 2 },
month = { October },
year = { 2014 },
issn = 0975-8887,
pages = { 33-38 },
numpages = 6,
url = { /proceedings/micro/number2/18321-1819/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Microelectronics, Circuits and Systems
%A Anindita Dash
%A Swetapadma Dash
%A S.k.mandal
%T Design of Optimized Wallace Tree Multiplier in Cadence
%J International Conference on Microelectronics, Circuits and Systems
%@ 0975-8887
%V MICRO
%N 2
%P 33-38
%D 2014
%I International Journal of Computer Applications
Abstract

Shrinking device size has been a major area of interest for VLSI design engineers. In order to achieve multiple functions on the same substrate using the standard technology, designers have to deal with the issues of area and power dissipation. So there is a pressing demand for designers to work in the area of optimization. In this paper, we propose to optimize a Wallace Tree multiplier. The multiplier was implemented at the circuit level of design abstraction with Virtuoso® tool in Cadence.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Vlsi Power Dissipation Optimization Wallace Tree Multiplier Fpm Cadence