CFP last date
22 April 2024
Reseach Article

Testing of GALS Components

Published on December 2018 by Deepali Basavaraj Koppad
International Conference on Microelectronic Circuit and System
Foundation of Computer Science USA
MICRO2017 - Number 1
December 2018
Authors: Deepali Basavaraj Koppad
7aa8110f-fd97-4542-a573-1d1acc5cd784

Deepali Basavaraj Koppad . Testing of GALS Components. International Conference on Microelectronic Circuit and System. MICRO2017, 1 (December 2018), 32-36.

@article{
author = { Deepali Basavaraj Koppad },
title = { Testing of GALS Components },
journal = { International Conference on Microelectronic Circuit and System },
issue_date = { December 2018 },
volume = { MICRO2017 },
number = { 1 },
month = { December },
year = { 2018 },
issn = 0975-8887,
pages = { 32-36 },
numpages = 5,
url = { /proceedings/micro2017/number1/30181-1629/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Microelectronic Circuit and System
%A Deepali Basavaraj Koppad
%T Testing of GALS Components
%J International Conference on Microelectronic Circuit and System
%@ 0975-8887
%V MICRO2017
%N 1
%P 32-36
%D 2018
%I International Journal of Computer Applications
Abstract

The purpose of this paper is to perform structural testing on GALS (Globally Asynchronous and Locally Synchronous) components, such as wrapper designs. GALS consists of three main parts: synchronous block, I/O ports and a local clock generator. The I/O Ports and the local clock generator form the wrapper design. Testing has been done for every net in each of the wrapper components. The feedback nets that are usually uncontrollable are also tested using same methodology. The collapse ratio and the maximum number of test vectors required are calculated for every component. A 2:1 mux is used to detect 3 faults that could not be detected using structural testing. Fault coverage of 100% is obtained for every component of the wrappers. The testing is performed on two different wrappers using Pyxis schematic in Mentor Graphics for 180 nm technology.

References
  1. J Muttersbach, T Villiger. Fichtner, Wolfgang, 2000 Practical design of globally asynchronous locally-synchronous systems, Proceedings of Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems 52-59.
  2. C Anju, Kiriti S Pande, 2012 Low power GALS interface implementation with stretchable clocking scheme, International Journal of Computer Science Issues IJCSI, vol. 9, Issue 4, no 3.
  3. Parag Lala 1997 Digital Circuit Testing and Testability The Morgan Kaufmann Series in Computer Architecture and Design Series, Academic Press.
  4. M. Bushnell, Vishwani Agrawal, 2002 Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Volume 17, Springer US Publication.
  5. Frank K. Gürkaynak, Thomas Villiger, Stephan Oetiker, Norbet F elber, HubertKaeslin, Wolfgang Fichtner, 2002 A Functional Test Methodology for GALS Systems Proceedings of the 8th International Symposium on Asynchronous Circuits and Systems ASYNC.
  6. S Zeidler; M Krsti´c, 2015 A survey about testing asynchronous circuits, European Conference Circuit Theory and Design ECCTD, 1-4, 24-26
  7. L Nagy, J Koscelansky, V Stopjakova, 2014 Design of a globally asynchronous locally synchronous digital system, IEEE 12th International Conference on Emerging eLearning Technologies and Applications ICETA, 529-533.
  8. M. Krsti´c and E. Grass, 2005 BIST technique for GALS systems, Proceedings of the 8th Euromicro Conference on Digital System Design DSD, 10–16.
  9. A. Efthymiou, 2010 Initialization-Based Test Pattern Generation for Asynchronous Circuits, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 4, 591-601.
  10. Akarsh Reddy Ravi, 2004 Globally asynchronous, locally synchronous wrapper configurations for point-to-point and multi-point data communication, M. S. Thesis, Dept. Electrical and Computer. Engineering, University of Central Florida, Orlando, Florida.
  11. D. L. Oliveira, T. Curtinhas, L. A. Faria and L. Romano, 2015 A novel asynchronous interface with pausible clock for partitioned synchronous modules, IEEE 6th Latin American Symposium, Montevideo, 1-4.
Index Terms

Computer Science
Information Sciences

Keywords

Gals Wrapper Testing Fault Coverage.