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Delay and Power Reduction in RLC VLSI Interconnect Models

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IJCA Proceedings on National Symposium on Modern Information and Communication Technologies for Digital India
© 2016 by IJCA Journal
MICTDI 2016 - Number 2
Year of Publication: 2016
Authors:
Aayushi Sharma
Dhriti Duggal

Aayushi Sharma and Dhriti Duggal. Article: Delay and Power Reduction in RLC VLSI Interconnect Models. IJCA Proceedings on National Symposium on Modern Information and Communication Technologies for Digital India MICTDI 2016(2):28-31, December 2016. Full text available. BibTeX

@article{key:article,
	author = {Aayushi Sharma and Dhriti Duggal},
	title = {Article: Delay and Power Reduction in RLC VLSI Interconnect Models},
	journal = {IJCA Proceedings on National Symposium on Modern Information and Communication Technologies for Digital India},
	year = {2016},
	volume = {MICTDI 2016},
	number = {2},
	pages = {28-31},
	month = {December},
	note = {Full text available}
}

Abstract

This paper presents a comparative analysis of reduced segment; T and ? RLC interconnect models. With down scaling of technology, the interconnect structures have became a predominant factor in determining the overall circuit performance. Controlling interconnect propagation delay is the fundamental parameter to high speed VLSI designs. In this work, model performance has been evaluated in terms of propagation delay and power dissipation. The design models have been implemented using Cadence Virtuoso Analog Design Suite at 180nm CMOS technology at high frequency range of 0. 1GHz to 2GHz. A significant decrease of 38. 424ps in propagation delay has been observed in ?-Model as compared to the reduced segment interconnect model. 7. 3253aW less power dissipation has been observed in reduced tree model when compared to RLC ?-Model.

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