Call for Paper - August 2020 Edition
IJCA solicits original research papers for the August 2020 Edition. Last date of manuscript submission is July 20, 2020. Read More

Multiplexer based Design for Ternary Logic Circuits

Print
PDF
IJCA Proceedings on National Conference on Electronics and Communication
© 2015 by IJCA Journal
NCEC 2015 - Number 1
Year of Publication: 2015
Authors:
Vani H.
Renuka Sagar
Rohini H. M.

Vani H., Renuka Sagar and Rohini H.m.. Article: Multiplexer based Design for Ternary Logic Circuits. IJCA Proceedings on National Conference on Electronics and Communication NCEC 2015(1):5-8, December 2015. Full text available. BibTeX

@article{key:article,
	author = {Vani H. and Renuka Sagar and Rohini H.m.},
	title = {Article: Multiplexer based Design for Ternary Logic Circuits},
	journal = {IJCA Proceedings on National Conference on Electronics and Communication},
	year = {2015},
	volume = {NCEC 2015},
	number = {1},
	pages = {5-8},
	month = {December},
	note = {Full text available}
}

Abstract

Three valued logic which is also called as a ternary logic is a best alternative to conventional binary logic. Ternary logic has got its own importance due to its energy efficiency resulting from reduced complexity of interconnect and chip area. This paper presents a methodology for the design of ternary multiplexer circuit and also the design of ternary logic circuits based on CMOS. Designing of ternary multiplexer is presented first. Later the proposed methodology for the design of ternary logic circuits is presented. This proposed design methodology is used to implement 1-bit half adder circuit using SPICE model. These new proposed implementations are compared with the old existing designs for the parameters like delay, power, number of transistors, power delay product etc. Simulation results indicate that the mux based 1-bit half adder design has reduced number of transistors, delay and power delay product when compared to the existing binary logic design.

References

  • K. C. Smith, "The prospects of multi-valued logic:A technology and application view," IEEE Trans. Cpmputer,vol. C-30,pp. 619,sep. 1981.
  • D. J. Porat,"Threevalueddigitalsystem",Proc. IEEE,vol. 116,pp. 946-954,june 1969.
  • Hurst, S. L. 'Multiple valued logic-its status and its future',IEEE Trans. ,1984,C-33,pp. 1160-1179.
  • A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits Jürgen Stock, Jörg Malindretos, Klaus Michael Indlekofer, Michael Pöttgens, Arno Förster, and Hans Lüth.
  • J. L. Huertas and J. M. Carmana,"Low power ternary CMOS circuits", in Proc. 9th Int. Symp. Multiple valued logic,Bath,England,1974,pp. 170-174.
  • Journal of Crystal Growth Volume 272, Issues 1–4, 10 December 2004, Pages 148–153 The Twelfth International Conference on Metalorganic Vapor Phase Epitaxy.
  • IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 4, NO. 2, MARCH 2005. Carbon-Nanotube-Based Voltage-Mode. Multiple-Valued Logic Design.
  • IEEE Journal of Solid-State Circuits (2007) 5. Alam, M. , Kang, K. , Paul, B. C. , Roy, K. : Reliability and Process –Variation Aware Design of VLSI Circuits.
  • ISDRS 2007, December 12-14, 2007, College Park, MD, USA . . . Device and Circuit Modeling using Novel 3-State Quantum Dot Gate FETs. F. C. Jain, E. Heller.
  • Appenzeller, J. Carbon nanotubes for high-performance electronics—progress and prospect. Proc. IEEE 96, 201–211 (2008).
  • X. W. Wu "CMOS Ternary logic circuits" IEEE Proceedings vol. 137,pt. g,No. 1. February 1990.