Digital Library Creation using Standard Cells Implemented using GPDK 180 Nm Technology

IJCA Proceedings on National Conference on Electronics and Communication
© 2015 by IJCA Journal
NCEC 2015 - Number 1
Year of Publication: 2015
Somshekhar R. Puranmath
Manu. T. M
Archana Kori
Sneha Meti

Somshekhar R Puranmath, Manu.t.m, Archana Kori and Sneha Meti. Article: Digital Library Creation using Standard Cells Implemented using GPDK 180 Nm Technology. IJCA Proceedings on National Conference on Electronics and Communication NCEC 2015(1):9-13, December 2015. Full text available. BibTeX

	author = {Somshekhar R. Puranmath and Manu.t.m and Archana Kori and Sneha Meti},
	title = {Article: Digital Library Creation using Standard Cells Implemented using GPDK 180 Nm Technology},
	journal = {IJCA Proceedings on National Conference on Electronics and Communication},
	year = {2015},
	volume = {NCEC 2015},
	number = {1},
	pages = {9-13},
	month = {December},
	note = {Full text available}


Physical design in VLSI circuits is getting more complex with increase in circuit complexity. The major troublesome job in physical design is the difficulties encountered in routing. In physical design of digital circuits optimization of area is more important unlike in analog circuits where performance is given more priority. In the process of optimization of area in digital circuits routing in higher blocks can get more sophisticated. Standard cells are used as leaf cells in designing of higher digital blocks where the height of the standard cells has to be optimum. Therefore it is necessary to carefully design the standard cells and also create an environment for easy creation of bigger blocks using these leaf cells with simple routing at the top level. In this paper, a standard cell library is created where the height of the cells is optimized and also there are well defined space defined for systematic routing. Using these cells bigger digital blocks is created which demonstrates that routing can be made simple at the top level. In VLSI front end design parameters like gain, bandwidth, voltage swing etc are considered as major constraints [8]. In case of physical design of VLSI circuit's area, pin placement, routing, power planning and the shape of the layouts are the design constraints. In this paper, rectangular shapes for the leaf cells are created and the area of every standard cell is optimized. This helps in creation of digital circuits where one can access the created library and use the leaf cells as instance hence saving the design time. Routing is simplified by defining tracks on which metals will be routed. Tracks are designed such that any two metals can be routed on horizontal tracks placed one below other without the need to check of DRC rules. This is ensured by pre-defining the tracks and placing them at minimum DRC space defined by the technology used. All the digital circuits are implemented using cmos technology and the pmos and nmos devices widths are selected such that they are both of equal strength. This also ensures equal rise and fall time. All circuits are simulated using spectre tool and physical designs are verified for DRC and LVS.


  • Jeannette Donan Djigbenou, Thien Van Nguyen, Cheng Wei Ren, and Dong Sam HaG. "Development of TSMC 0. 25?m Standard Cell Library," 1-4244-1029-0/07/ 2007 IEEE.
  • Wofgang Roethig ,"Library Characterization and Modeling for 130 and 90 nm Soc Design,IEEE Soc. Conference,". Nec Electronics America. CA,USA, 17-20 Sept. 2003, 383–386p.
  • Patrick H. Madden. "Reporting of Standard Cell placement results," IEEE transactions on computer-aided design of integrated circuits and systems, vol. 21, no. 2, february2002.
  • Suri Uppalapati, "Low power design of standard cell digital vlsi circuits,"New Brunswick Rutgers,The State university of New Jersey,New Jersey, october 2004.
  • Carl F. Nielsen and Samuel R. Girgis " WPI 0. 5mm CMOS Standard cell Library Databook," Microelectronics Group , April 2000
  • Alfred E. Dunlop, Brain W. Kernighan, "Procedure for placement of standard-cell VLSI circuits", IEEE transactions on computer-aided design, Vol. CAD-4, No. 1, January 1985.
  • Sung-Mo Kang, Yusuf Leblebici, "CMOS Digital integrated circuits- analysis and design," 3rd edition.
  • Alan Hastings, "The art of analog layout," Prentice Hall,Upper saddle river, New Jersey.
  • R. Jacob Baker,"CMOS Circuit Design, Layout and Simulation," 3rd Edition, Wiley publications.
  • Prof. Poornima H S, Prof. Chethana K S "Standard Cell Library Design and Characterization using 45nm technology" IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 1, Ver. I (Jan. 2014), PP 29-33.