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VLSI Design, Implementation and Verification of Scalable FFT Processor

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IJCA Proceedings on National Conference on Electronics, Signals and Communication
© 2018 by IJCA Journal
NCESC 2017 - Number 3
Year of Publication: 2018
Authors:
Mohammed Irfan M
Naseer Uddin

Mohammed Irfan M and Naseer Uddin. Article: VLSI Design, Implementation and Verification of Scalable FFT Processor. IJCA Proceedings on National Conference on Electronics, Signals and Communication NCESC 2017(3):15-19, July 2018. Full text available. BibTeX

@article{key:article,
	author = {Mohammed Irfan M and Naseer Uddin},
	title = {Article: VLSI Design, Implementation and Verification of Scalable FFT Processor},
	journal = {IJCA Proceedings on National Conference on Electronics, Signals and Communication},
	year = {2018},
	volume = {NCESC 2017},
	number = {3},
	pages = {15-19},
	month = {July},
	note = {Full text available}
}

Abstract

This paper presents designand implementation of a Pipelined FFT Architecture using Verilog HDL. The Pipelined Architectureis implemented using RS2DF(Radix-2 Single path Delay Feedback). Standard FPGA Flow is adapted to implement and was programmed on Spartan 3AN FPGA. Simulations and Synthesis are carried using Modelsim and Xilinx ISE. The Verilog Simulations resultsare compared with Inbuilt MATLAB FFT Core for verification of the design. The Speed achieved for this Core is 87. 15 MHz

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