Notification: Our email services are now fully restored after a brief, temporary outage caused by a denial-of-service (DoS) attack. If you sent an email on Dec 6 and haven't received a response, please resend your email.
CFP last date
20 December 2024
Reseach Article

Design and Performance Evaluation of Reconfigurable Architecture of FIR Filter for Signal Processing Applications

Published on July 2018 by Veenashree Hiremath
National Conference on Electronics, Signals and Communication
Foundation of Computer Science USA
NCESC2017 - Number 4
July 2018
Authors: Veenashree Hiremath
c3418432-9cb0-434d-91d3-ae55c0f05f1a

Veenashree Hiremath . Design and Performance Evaluation of Reconfigurable Architecture of FIR Filter for Signal Processing Applications. National Conference on Electronics, Signals and Communication. NCESC2017, 4 (July 2018), 4-6.

@article{
author = { Veenashree Hiremath },
title = { Design and Performance Evaluation of Reconfigurable Architecture of FIR Filter for Signal Processing Applications },
journal = { National Conference on Electronics, Signals and Communication },
issue_date = { July 2018 },
volume = { NCESC2017 },
number = { 4 },
month = { July },
year = { 2018 },
issn = 0975-8887,
pages = { 4-6 },
numpages = 3,
url = { /proceedings/ncesc2017/number4/29627-7123/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on Electronics, Signals and Communication
%A Veenashree Hiremath
%T Design and Performance Evaluation of Reconfigurable Architecture of FIR Filter for Signal Processing Applications
%J National Conference on Electronics, Signals and Communication
%@ 0975-8887
%V NCESC2017
%N 4
%P 4-6
%D 2018
%I International Journal of Computer Applications
Abstract

Finite impulse response (FIR) filters are tremendously used in signal processing applications like RADAR processing, noise cancellation, biomedical imaging, removing DC component in signal etc. Most of Digital signal processing algorithm such as FFT,FIR and IIR are now implemented on FPGA because it offers very attractive solutions than any other in terms area ,power and speed. Reconfigurable architecture used in this paper is Distributed arithmetic . Here DA based FIR filter implemented on vertex5 with device XC5VLX110T. DA based FIR filter proposes advancement in speed, performance and area.

References
  1. H. s. o. Migdadi, R. A. Abd-Alhameed, H. A. Obeidat,"FIR implementation on FPGA :Investigate FIR order on SDA and PDA " IEEE publication.
  2. Sang Yoon Park, Member, IEEE and Pramod Kumar Meher, Senior Member, IEEE " Efficient FPGA and ASIC realization of DA based reconfigurable FIR digital filter "IEEE transction on circuit .
  3. Yajun Zhou, Pingzheng Shi School of Automation, HangZhou Dianzi University "distributed arithmetic for FIR filter implementation on FPGA. 978-1-61284-774-0/11/$26IEEE.
  4. Saliha Harize?, Mohamed Benouaret, Noureddine DoghmaneB "A methodology for implementating decimator FIR filters on FPGA" ELSEVIER publication.
  5. J. L. MAZHER IQBAL. And S. VARADARAJAN,"New approach to memory less design and look up table realization for low complexity reconfigurable Digital filter architecture"WSEAS transctions on system.
Index Terms

Computer Science
Information Sciences

Keywords

Da-distributed Arithmetic Fpga-field Programmable Gate Array Radar –radio Direction And Ranging.