This paper presents a CMOS Nyquist rate Current Steering DAC using segmented architecture for wireless application. Segmentation is used to improve the dynamic behavior of the converter but comes at a cost. The proposed DAC adapts 8-4 segmentation architecture to achieve high speed. The DAC is realized in 0.18-μm CMOS process and the power supply used is 1.8V. Cadence Virtuoso Schematic editor is used for drawing the schematic of various circuits and the circuits are simulated using Virtuoso circuit simulator. The dac has been simulated and found to be working satisfactorily.

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DAC Unit current source DNL glitch clock skew clock feedthrough