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Reseach Article

Design and Implementation of Energy Efficient Approximate Multiplier

Published on September 2015 by B. Anish Fathima, C. Vasanthanayaki
National Conference on Information and Communication Technologies
Foundation of Computer Science USA
NCICT2015 - Number 1
September 2015
Authors: B. Anish Fathima, C. Vasanthanayaki
ddc069a0-b56c-426d-894d-95f1626699dd

B. Anish Fathima, C. Vasanthanayaki . Design and Implementation of Energy Efficient Approximate Multiplier. National Conference on Information and Communication Technologies. NCICT2015, 1 (September 2015), 19-23.

@article{
author = { B. Anish Fathima, C. Vasanthanayaki },
title = { Design and Implementation of Energy Efficient Approximate Multiplier },
journal = { National Conference on Information and Communication Technologies },
issue_date = { September 2015 },
volume = { NCICT2015 },
number = { 1 },
month = { September },
year = { 2015 },
issn = 0975-8887,
pages = { 19-23 },
numpages = 5,
url = { /proceedings/ncict2015/number1/22347-1538/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on Information and Communication Technologies
%A B. Anish Fathima
%A C. Vasanthanayaki
%T Design and Implementation of Energy Efficient Approximate Multiplier
%J National Conference on Information and Communication Technologies
%@ 0975-8887
%V NCICT2015
%N 1
%P 19-23
%D 2015
%I International Journal of Computer Applications
Abstract

Modern Digital signal processing and image processing applications are aiming towards energy efficiency. The prime arithmetic operation performed for these processes is multiplication. Hence energy efficiency of multiplication is critical. Since many digital applications use fixed- point arithmetic, it exhibits computational error tolerance. In this brief, a multiplier is proposed that can trade-off computational accuracy with energy consumption. Segmenting the original operands with significant bits and performing the multiplication only for those segments is the main principle. The proposed method of approximate multiplier consumes lesser power and hence notably lesser energy with average computational error of ~1%, when compared to the existing approximate multipliers with similar principle. Further optimization of the proposed multiplier is also done which improves the average computational accuracy along with a considerable reduction in the area consumed by the proposed multiplier.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Vlsi Embedded Systems Integrated Circuits Dsp