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Design of Multiplier based Low Power PID Controllers

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IJCA Proceedings on National Conference on Information and Communication Technologies
© 2015 by IJCA Journal
NCICT 2015 - Number 1
Year of Publication: 2015
Authors:
V. Priya
A. Abinaya

V Priya and A Abinaya. Article: Design of Multiplier based Low Power PID Controllers. IJCA Proceedings on National Conference on Information and Communication Technologies NCICT 2015(1):34-37, September 2015. Full text available. BibTeX

@article{key:article,
	author = {V. Priya and A. Abinaya},
	title = {Article: Design of Multiplier based Low Power PID Controllers},
	journal = {IJCA Proceedings on National Conference on Information and Communication Technologies},
	year = {2015},
	volume = {NCICT 2015},
	number = {1},
	pages = {34-37},
	month = {September},
	note = {Full text available}
}

Abstract

The increasing industrial growth needs its system to be fully controllable. Such control systems are almost composed of VLSI components such as adders, multipliers and accumulators. This paper analyzes two MAC units with array, booth algorithms and those blocks are incorporated in PID controller architecture. Comparisons are made with power consumption of each architecture. The simulations are done in Modelsim and power results are synthesized using Xilinx ISE. The results suggest that the PID controller with booth based MAC unit and PID architecture consumes less power when compared to array based architectures.

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