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Placement Compelled Steering Algorithm for Wire length Minimization in FPGA

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IJCA Proceedings on National Conference on Information and Communication Technologies
© 2015 by IJCA Journal
NCICT 2015 - Number 2
Year of Publication: 2015
Authors:
Khaavya S. L.
S. Umamaheswari

Khaavya S.l. and S Umamaheswari. Article: Placement Compelled Steering Algorithm for Wire length Minimization in FPGA. IJCA Proceedings on National Conference on Information and Communication Technologies NCICT 2015(2):32-35, September 2015. Full text available. BibTeX

@article{key:article,
	author = {Khaavya S.l. and S. Umamaheswari},
	title = {Article: Placement Compelled Steering Algorithm for Wire length Minimization in FPGA},
	journal = {IJCA Proceedings on National Conference on Information and Communication Technologies},
	year = {2015},
	volume = {NCICT 2015},
	number = {2},
	pages = {32-35},
	month = {September},
	note = {Full text available}
}

Abstract

Placements of logical blocks in FPGA use many optimization algorithms in heuristic manner. Main objective is to provide minimization in wire length during the task placement inside Reconfigurable FPGAs, which will decrease the area, power and delay and increase the speed of execution. Optimization algorithms are applied in the Benchmark circuits and the results are compared. Due to the technological advancement, density of the devices increases so that necessitates improvement in minimization of wire length. Hence this project, proposes an optimum solution for wire length minimization.

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