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Reseach Article

Placement Compelled Steering Algorithm for Wire length Minimization in FPGA

Published on September 2015 by Khaavya S.l., S. Umamaheswari
National Conference on Information and Communication Technologies
Foundation of Computer Science USA
NCICT2015 - Number 2
September 2015
Authors: Khaavya S.l., S. Umamaheswari
d93d8041-323f-4d66-809c-2a3140f71d5b

Khaavya S.l., S. Umamaheswari . Placement Compelled Steering Algorithm for Wire length Minimization in FPGA. National Conference on Information and Communication Technologies. NCICT2015, 2 (September 2015), 32-35.

@article{
author = { Khaavya S.l., S. Umamaheswari },
title = { Placement Compelled Steering Algorithm for Wire length Minimization in FPGA },
journal = { National Conference on Information and Communication Technologies },
issue_date = { September 2015 },
volume = { NCICT2015 },
number = { 2 },
month = { September },
year = { 2015 },
issn = 0975-8887,
pages = { 32-35 },
numpages = 4,
url = { /proceedings/ncict2015/number2/22357-1554/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on Information and Communication Technologies
%A Khaavya S.l.
%A S. Umamaheswari
%T Placement Compelled Steering Algorithm for Wire length Minimization in FPGA
%J National Conference on Information and Communication Technologies
%@ 0975-8887
%V NCICT2015
%N 2
%P 32-35
%D 2015
%I International Journal of Computer Applications
Abstract

Placements of logical blocks in FPGA use many optimization algorithms in heuristic manner. Main objective is to provide minimization in wire length during the task placement inside Reconfigurable FPGAs, which will decrease the area, power and delay and increase the speed of execution. Optimization algorithms are applied in the Benchmark circuits and the results are compared. Due to the technological advancement, density of the devices increases so that necessitates improvement in minimization of wire length. Hence this project, proposes an optimum solution for wire length minimization.

References
  1. Shobana. V, Nagalakshmi Venuopal, Efficient placement Driven Routing Algorithm for FPGA using
  2. PSO , International Journal of Engineering Research & Technology, Vol. 3, Issue 5, pp. 350-355, May-2014. Xin-Sha Yang, Suash Deb, Cuckoo Search: Recent Advantages And Applications ,Sprinjer,Vol. 24, pp. 169-174,February-2013.
  3. Tarun Bali, Mamta Khosla, Naveed Anjum,
  4. Placement in FPGA using Hybrid PSO-SA Technique , International Journal of EngineeringResearch & Technology, Vol. 2, Issue 9, pp. 1553-1556, September-2013. Sangita Roy, Sheli Sinha Chaudri, Cuckoo Search Algorithm Using Levy Flight: Review , I. J Modern
  5. Education of Computer and Information Technology (IJCIT), Vol. 12, pp. 10-15, December-2013. Mohammed El-Abd, Hassan Hassan, Mohab Anis, Mohamed S. Kamel,Mohammed lmasry, Discrete Cooperative Particle Swarm Optimization for FPGA
  6. Placements , Elsevier, Vol. 10, pp. 284-295, September 2010. Emad Elbeltagi,Tarek Hegazy, Donald Grieson, Comparison among Five Evolutionary Based Optimization Algorithms , Elsevier, Vol. 19, pp. 43-53, January 2005.
  7. Pinar Civicioglu,Erkan Besdok A conceptual comparison of the Cuckoo-search, particle swarm optimization, differential evolution and artificial bee colony algorithms ,Springer, Vol. 21,pp. 315-146, July 2013.
  8. Xin-She Yanga,n, Suash Deb, Multiobjective cuckoo search for design optimization, Elsevier, Vol. 32, pp. 1616-1624, October 2011
Index Terms

Computer Science
Information Sciences

Keywords

Fpgas Optimization Algorithm