In this paper the design and implementation of 32 bit IEEE 754 single precision floating point FFT architecture is proposed. Usually for FFT calculation the sequential circuits use for mantissa adjustment which is somewhat tedious job So, new approach is define for calculating FFT in pure combinational circuits form. The simulation result are compare with the quartus II and Active HDL software also it is cross verified with Matlab . The algorithm is implemented on FPGA

1. E. O. Brigham, The fast Fourier transform and its applications, Prentice Hall, 1988.
2. J. G. Pmakis, Digital signal processing: principles algorithms, and applications., Prentice-Hall Intemational, 1996.
3. H. Hu, T. Jin, X. Zhang, Z. Lu, Z. Qian, _ A Floating-point Coprocessor Configured by a FPGA in a Digital Platform Based on Fixed-point DSP for Power Electronics_, IEEE IPEMC_2006
4. ShengmeiMou,XiaodongYang “Design of a high –speed FPGA-based 32-bit floating point FFT Processor” 2007 IEEE.
5. Floating –point FFT Processor (IEEE 754 single presion Radix 2 core,White Paper from altera)
6. Shiqun Zheng Dunshan Yu,”Design and implimention of a parrel real-time FFT Processor”,7 th IEEE conference on Solid – State and Integated Circuits Technology,Vol.3,pp,1665- 168,Oct2004.
7. Bin Zhou ,David Hwang “ Implementations and Optimizations of pipeline FFTs on Xilinx FPGAs.(2008 International Conference on Reconfigurable computing and FPGAs)
8. M.Hasan & T. Arslan “Coefficient Memory Addressing scheme for VLSI Implementation of FFT Processor”[IEEE 2000 Scotland].

IEEE Floating-point FPGA FFT HDL