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Reseach Article
Current Starved Voltage Controlled Oscillator for PLL Using 0.18?m CMOS Process
| 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013) |
| Foundation of Computer Science USA |
| NCIPET - Number 3 |
| March 2012 |
| Authors: Rashmi K Patil, Vrushali G Nasre |
| 8d2ae817-e1df-40ba-8a32-74b1b81fe573 |
Rashmi K Patil, Vrushali G Nasre . Current Starved Voltage Controlled Oscillator for PLL Using 0.18?m CMOS Process. 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013). NCIPET, 3 (March 2012), 23-25.
Abstract
A five stage current starved Voltage Controlled Oscillator (CMOS VCO) is designed in this paper. The design is implemented in Tanner environment with high oscillation frequency and low power consumption. Oscillation frequency of the designed VCO ranges from 25.70 MHz to 222.53 MHz. The circuit is simulated using 180nm SCN018 Technology. Simulation results reported that the power consumption is 58.47uA @ 1.8V VDD. Design procedures and simulation results are illustrated. This design is suitable for PLL as a frequency multiplier.
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