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Current Starved Voltage Controlled Oscillator for PLL Using 0.18m CMOS Process

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IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012)
© 2012 by IJCA Journal
ncipet - Number 3
Year of Publication: 2012
Authors:
Rashmi K Patil
Vrushali G Nasre

Rashmi K Patil and Vrushali G Nasre. Article: Current Starved Voltage Controlled Oscillator for PLL Using 0.18?m CMOS Process. IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012) ncipet(3):-, March 2012. Full text available. BibTeX

@article{key:article,
	author = {Rashmi K Patil and Vrushali G Nasre},
	title = {Article: Current Starved Voltage Controlled Oscillator for PLL Using 0.18?m CMOS Process},
	journal = {IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012)},
	year = {2012},
	volume = {ncipet},
	number = {3},
	pages = {-},
	month = {March},
	note = {Full text available}
}

Abstract

A five stage current starved Voltage Controlled Oscillator (CMOS VCO) is designed in this paper. The design is implemented in Tanner environment with high oscillation frequency and low power consumption. Oscillation frequency of the designed VCO ranges from 25.70 MHz to 222.53 MHz. The circuit is simulated using 180nm SCN018 Technology. Simulation results reported that the power consumption is 58.47uA @ 1.8V VDD. Design procedures and simulation results are illustrated. This design is suitable for PLL as a frequency multiplier.

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