Call for Paper - August 2019 Edition
IJCA solicits original research papers for the August 2019 Edition. Last date of manuscript submission is July 20, 2019. Read More

Design Methods for Low-Power Implementation

Print
PDF
IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012)
© 2012 by IJCA Journal
ncipet - Number 7
Year of Publication: 2012
Authors:
N. A. Mohota
T. N. Mohota

N A Mohota and T N Mohota. Article: Design Methods for Low-Power Implementation. IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012) ncipet(7):23-25, March 2012. Full text available. BibTeX

@article{key:article,
	author = {N. A. Mohota and T. N. Mohota},
	title = {Article: Design Methods for Low-Power Implementation},
	journal = {IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012)},
	year = {2012},
	volume = {ncipet},
	number = {7},
	pages = {23-25},
	month = {March},
	note = {Full text available}
}

Abstract

Implementation of low power techniques in the design is increasing because of the increasing clock frequency and a continuous increase in the number of transistors on chip. These low power techniques are being implemented across all levels of abstraction - system level to device level. Here, approaches related to front-end HDL based design styles, which can reduce power consumption, have been mentioned. As is known, power dissipation has a direct relation with the clock frequency and dynamic power also depends upon the rate at which the data toggles for a given circuit. The design styles mentioned here, focus on several areas of designing using HDL, which are at times not considered significant, as they do not affect the functionality. The techniques mentioned here are quite simple to implement and mostly clear of confusion techniques that are considered quite insignificant, yet have a significant impact on the overall power-consumption.

References

  • Roger Woods, John McAllister, Gaye Lightbody and Ying Yi, "FPGA implementation of signal processing systems", Wiley, 2008.
  • Mircea R. Stan and Wayne P. Burleson, "Bus Invert Coding for Low-Power I/O", IEEE Transactions on VLSI systems, Vol.3, No. 1, March 1995, pp 49 – 58.
  • Hichem Belhadj, Vishal Aggrawal, Ajay Pradhan, Amal Zerrouki, "Power Aware FPGA design – Part 3", Programmable Logic Design Line, 17th February, 2009.
  • Gary Yeap, "Practical Low power Digital VLSI design", Kluwer Academic Publishers, 1998.