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Review on Design of Floating Point FFT Processor using VHDL

IJCA Proceedings on National Conference on Recent Trends in Computer Science and Information Technology
© 2016 by IJCA Journal
NCRTCSIT 2016 - Number 1
Year of Publication: 2016
Roshan Pahune
A. P. Rathkanthiwar

Roshan Pahune and A P Rathkanthiwar. Article: Review on Design of Floating Point FFT Processor using VHDL. IJCA Proceedings on National Conference on Recent Trends in Computer Science and Information Technology NCRTCSIT 2016(1):6-8, June 2016. Full text available. BibTeX

	author = {Roshan Pahune and A. P. Rathkanthiwar},
	title = {Article: Review on Design of Floating Point FFT Processor using VHDL},
	journal = {IJCA Proceedings on National Conference on Recent Trends in Computer Science and Information Technology},
	year = {2016},
	volume = {NCRTCSIT 2016},
	number = {1},
	pages = {6-8},
	month = {June},
	note = {Full text available}


The design approach of FFT algorithm for floating point numbers is investigated in this paper. Using Fast Fourier Transform (FFT), the Discrete Fourier Transform (DFT) can be implement very fast. The FFT can be design by radix-2 butterfly algorithm using Decimatiom in Time (DIT) or Decimation in Frequency (DIF) methods . Using IEEE-754 Single precision floating point and Double precision floating-point format the Fast Fourier Transform (FFT) for floating point numbers can be easily computed and simulated using VHDL tools. The floating point number can support wide range of values. It can be represented using three fields sign, exponent and mantissa. The floating point Single precision format is always 32 bit and floating point Double precision format is always 64 bit. In this paper floating point addition, subtraction and multiplication algorithms is used. The IEEE-754 converter is used to convert decimal floating point number into Binary floating point format and it is also useful to verify the result. The floating point FFT processor reduce complexity of computation ,area, delay and power consumption.


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