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Review on Design Of 16-Bit Quaternary Adder using Various Encoding Techniques

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IJCA Proceedings on National Conference on Recent Trends in Computer Science and Information Technology
© 2016 by IJCA Journal
NCRTCSIT 2016 - Number 1
Year of Publication: 2016
Authors:
Gaurav M. Kathalkar
Vaishali Raut

Gaurav M Kathalkar and Vaishali Raut. Article: Review on Design Of 16-Bit Quaternary Adder using Various Encoding Techniques. IJCA Proceedings on National Conference on Recent Trends in Computer Science and Information Technology NCRTCSIT 2016(1):9-11, June 2016. Full text available. BibTeX

@article{key:article,
	author = {Gaurav M. Kathalkar and Vaishali Raut},
	title = {Article: Review on Design Of 16-Bit Quaternary Adder using Various Encoding Techniques},
	journal = {IJCA Proceedings on National Conference on Recent Trends in Computer Science and Information Technology},
	year = {2016},
	volume = {NCRTCSIT 2016},
	number = {1},
	pages = {9-11},
	month = {June},
	note = {Full text available}
}

Abstract

I am designing a 16 bit quaternary adder. Outline of the parallel rationale circuits is restricted by the necessity of the interconnections. A conceivable arrangement could be touched base at by utilizing a bigger arrangement of signs over the same chip region. Quaternary outlines are picking up significance from that point of view. It shows numerous esteemed full viper circuits, actualized in quaternary rationale. This is planned by utilizing one hot encoding and barrel shifter to accomplished Optimization in zone, speed and power will be accomplished by CMOS quaternary rationale. Sum and convey are handled in two separate squares, controlled by code generator unit. The circuit level execution of the different esteemed rationale administrators: legitimate aggregate, consistent item, level-up, level-down and level transformations are exhibited. Plan check will be done by Tanner Tools.

References

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