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Reseach Article

Design of Multinode Reconfigurable Network based Multiprocessor Systems on Chip

Published on April 2015 by Archana Gomkar
National Conference on Recent Trends in Information Security
Foundation of Computer Science USA
NCRTIS2015 - Number 1
April 2015
Authors: Archana Gomkar
5e4f3630-c4fd-4e19-a29e-8199da9819f6

Archana Gomkar . Design of Multinode Reconfigurable Network based Multiprocessor Systems on Chip. National Conference on Recent Trends in Information Security. NCRTIS2015, 1 (April 2015), 19-24.

@article{
author = { Archana Gomkar },
title = { Design of Multinode Reconfigurable Network based Multiprocessor Systems on Chip },
journal = { National Conference on Recent Trends in Information Security },
issue_date = { April 2015 },
volume = { NCRTIS2015 },
number = { 1 },
month = { April },
year = { 2015 },
issn = 0975-8887,
pages = { 19-24 },
numpages = 6,
url = { /proceedings/ncrtis2015/number1/20111-4005/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on Recent Trends in Information Security
%A Archana Gomkar
%T Design of Multinode Reconfigurable Network based Multiprocessor Systems on Chip
%J National Conference on Recent Trends in Information Security
%@ 0975-8887
%V NCRTIS2015
%N 1
%P 19-24
%D 2015
%I International Journal of Computer Applications
Abstract

Multi-Processor System on Chip (MPSoC) platforms are becoming increasingly more heterogeneous and are shifting towards a more communication-centric methodology. Net-works on Chip (NoC) have emerged as the design paradigm for scalable on-chip communication architectures. As the system complexity grows, the problem emerges as how to design and instantiate such a NoC-based MPSoC platform in a systematic and automated way. In this paper we present an integrated flow to automatically generate a highly configurable NoC-based MPSoC for FPGA instantiation. The system specification is done on a high level of abstraction, relieving the designer of error-prone and time consuming work. The flow uses the state-of-the-art Æthereal NoC, and Silicon Hive processing cores, both configurable at design- and run-time. We use this flow to generate a range of sample de-signs whose functionality has been verified on a Celoxica RC300E development board. The board, equipped with a Xilinx Virtex II 6000, also offers a huge number of periph-erals, and we show how their insertion is automated in the design for easy debugging and prototyping.

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Index Terms

Computer Science
Information Sciences

Keywords

Multiprocessor Multinode Reconfigurable Network Network On Chip And Soc Mode