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Nibble Mode Realization of Parallel CRC

Published on None 2011 by Sulipta Das, Devashree Mahato, Durga Prasad Dash
journal_cover_thumbnail

2nd National Conference on Computing, Communication and Sensor Network
Foundation of Computer Science USA
CCSN - Number 3
None 2011
Authors: Sulipta Das, Devashree Mahato, Durga Prasad Dash
4445e60b-1713-4e3b-be59-41c4c0396977

Sulipta Das, Devashree Mahato, Durga Prasad Dash . Nibble Mode Realization of Parallel CRC. 2nd National Conference on Computing, Communication and Sensor Network. CCSN, 3 (None 2011), 5-8.

@article{
author = { Sulipta Das, Devashree Mahato, Durga Prasad Dash },
title = { Nibble Mode Realization of Parallel CRC },
journal = { 2nd National Conference on Computing, Communication and Sensor Network },
issue_date = { None 2011 },
volume = { CCSN },
number = { 3 },
month = { None },
year = { 2011 },
issn = 0975-8887,
pages = { 5-8 },
numpages = 4,
url = { /specialissues/ccsn/number3/4181-ccsn018/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 2nd National Conference on Computing, Communication and Sensor Network
%A Sulipta Das
%A Devashree Mahato
%A Durga Prasad Dash
%T Nibble Mode Realization of Parallel CRC
%J 2nd National Conference on Computing, Communication and Sensor Network
%@ 0975-8887
%V CCSN
%N 3
%P 5-8
%D 2011
%I International Journal of Computer Applications
Abstract

This paper presents a parallel Cyclic Redundancy Check (CRC) architecture for IEEE 802.3u Medium Access Control (MAC) transmitter using data flow modelling. The purpose of the design is to improve the processing speed of data frames over fast ethernet Local Area Network (LAN). The input to the designed circuit is in nibble format. Synthesis options are explored along with Verilog Hardware Description Language (HDL) styles to have a balance among area and speed optimization in Xilinx ISE 12.1 tool. It is verified that the processing of MAC frames is faster in case of parallel CRC than the serial one. We investigate the inverse relationship between resource utilization and frequency of operation. A Critical Path Delay (CPD) of 3.801ns is achieved for parallel CRC implementation on Spartan3E XC3S100E-4-VQ100 Field Programmable Gate Array (FPGA). The behaviour of the design is analysed on target devices of Virtex6, Spartan6 and Virtex5 families of FPGA. It is found that Virtex6 XC6VLX75T-3-FF484 (40 nm technology) device offers the highest operating frequency of 1203.804 MHz allocating 32 Look Up Tables (LUTs) and 32 slices.

References
  1. G. W. Stallings, Data And Computer Communications, Prentice Hall, 2009.
  2. Behrouz A. Forouzan, Data Communications And Networking, Tata McGraw-Hill, 2009.
  3. G. Campobello, G. Patane, M. Russo, “Parallel CRC Realization”, IEEE Transactions On Computers, October 2003,Vol.52, No. 10, pp. 245-256.
  4. Tong-Bi Pei, Charles Zukowski, “High-speed Parallel CRC Circuits in VLSI”, IEEE Transactions On Communications, April 1992,Vol.40, No. 4, pp. 456-467.
  5. Chris Borrelli, “IEEE 802.3 Cyclic Redundancy Check”, XAPP209 (v1.0), March 23, 2001.
  6. M. Morris Mano, Digital design, Prentice Hall, 2007.
  7. Samir Palnitkar, Verilog HDL, Pearson Educatin, 2008.
Index Terms

Computer Science
Information Sciences

Keywords

Ethernet MAC frame Nibble Parallel CRC-32 Modulo-2 arithmetic Data flow modeling LFSR LUTs