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Low Power Test Pattern Generator for System on Chip Architecture

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IJCA Special Issue on International Conference on Computing, Communication and Sensor Network
© 2013 by IJCA Journal
CCSN2012 - Number 2
Year of Publication: 2013
Authors:
Ajit Kumar Mohanty
Biswanath Pratap Sahu
Chandan Patnaik
S. S. Mahato

Ajit Kumar Mohanty, Biswanath Pratap Sahu, Chandan Patnaik and S S Mahato. Article: Low Power Test Pattern Generator for System on Chip Architecture. IJCA Special Issue on International Conference on Computing, Communication and Sensor Network CCSN2012(2):11-15, March 2013. Full text available. BibTeX

@article{key:article,
	author = {Ajit Kumar Mohanty and Biswanath Pratap Sahu and Chandan Patnaik and S. S. Mahato},
	title = {Article: Low Power Test Pattern Generator for System on Chip Architecture},
	journal = {IJCA Special Issue on International Conference on Computing, Communication and Sensor Network},
	year = {2013},
	volume = {CCSN2012},
	number = {2},
	pages = {11-15},
	month = {March},
	note = {Full text available}
}

Abstract

Low Power test pattern generator using a linear feedback shift register (LFSR), called LP-TGP is presented to reduce the average and peak power of a circuit during test. The correlation between two test patterns generated by LP-TPG is more than between the random patterns. The goal of having intermediate patterns is to reduce the transitional activities of primary inputs which reduces the switching activities inside the circuit under test and hence power consumption. An experimental result shows that proposed method gives 30. 87% reduction in power during testing.

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