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Low Power Test Pattern Generator for System on Chip Architecture
| International Conference on Computing, Communication and Sensor Network |
| Foundation of Computer Science USA |
| CCSN2012 - Number 2 |
| March 2013 |
| Authors: Ajit Kumar Mohanty, Biswanath Pratap Sahu, Chandan Patnaik, S. S. Mahato |
| cfd2b1be-b870-4e1f-8a7e-3d76353f88aa |
Ajit Kumar Mohanty, Biswanath Pratap Sahu, Chandan Patnaik, S. S. Mahato . Low Power Test Pattern Generator for System on Chip Architecture. International Conference on Computing, Communication and Sensor Network. CCSN2012, 2 (March 2013), 11-15.
Abstract
Low Power test pattern generator using a linear feedback shift register (LFSR), called LP-TGP is presented to reduce the average and peak power of a circuit during test. The correlation between two test patterns generated by LP-TPG is more than between the random patterns. The goal of having intermediate patterns is to reduce the transitional activities of primary inputs which reduces the switching activities inside the circuit under test and hence power consumption. An experimental result shows that proposed method gives 30. 87% reduction in power during testing.
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