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Reseach Article

Low Power Test Pattern Generator for System on Chip Architecture

Published on March 2013 by Ajit Kumar Mohanty, Biswanath Pratap Sahu, Chandan Patnaik, S. S. Mahato
International Conference on Computing, Communication and Sensor Network
Foundation of Computer Science USA
CCSN2012 - Number 2
March 2013
Authors: Ajit Kumar Mohanty, Biswanath Pratap Sahu, Chandan Patnaik, S. S. Mahato
cfd2b1be-b870-4e1f-8a7e-3d76353f88aa

Ajit Kumar Mohanty, Biswanath Pratap Sahu, Chandan Patnaik, S. S. Mahato . Low Power Test Pattern Generator for System on Chip Architecture. International Conference on Computing, Communication and Sensor Network. CCSN2012, 2 (March 2013), 11-15.

@article{
author = { Ajit Kumar Mohanty, Biswanath Pratap Sahu, Chandan Patnaik, S. S. Mahato },
title = { Low Power Test Pattern Generator for System on Chip Architecture },
journal = { International Conference on Computing, Communication and Sensor Network },
issue_date = { March 2013 },
volume = { CCSN2012 },
number = { 2 },
month = { March },
year = { 2013 },
issn = 0975-8887,
pages = { 11-15 },
numpages = 5,
url = { /specialissues/ccsn2012/number2/10853-1015/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 International Conference on Computing, Communication and Sensor Network
%A Ajit Kumar Mohanty
%A Biswanath Pratap Sahu
%A Chandan Patnaik
%A S. S. Mahato
%T Low Power Test Pattern Generator for System on Chip Architecture
%J International Conference on Computing, Communication and Sensor Network
%@ 0975-8887
%V CCSN2012
%N 2
%P 11-15
%D 2013
%I International Journal of Computer Applications
Abstract

Low Power test pattern generator using a linear feedback shift register (LFSR), called LP-TGP is presented to reduce the average and peak power of a circuit during test. The correlation between two test patterns generated by LP-TPG is more than between the random patterns. The goal of having intermediate patterns is to reduce the transitional activities of primary inputs which reduces the switching activities inside the circuit under test and hence power consumption. An experimental result shows that proposed method gives 30. 87% reduction in power during testing.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Built-in Self-test Low Power Single Input Pattern Testing Switching Activity