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Design of User Define Instruction Set using APU

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IJCA Special Issue on International Conference on Computing, Communication and Sensor Network
© 2013 by IJCA Journal
CCSN2012 - Number 2
Year of Publication: 2013
Authors:
Pratap Khuntia
Soumyashree Sethy

Pratap Khuntia and Soumyashree Sethy. Article: Design of User Define Instruction Set using APU. IJCA Special Issue on International Conference on Computing, Communication and Sensor Network CCSN2012(2):19-23, March 2013. Full text available. BibTeX

@article{key:article,
	author = {Pratap Khuntia and Soumyashree Sethy},
	title = {Article: Design of User Define Instruction Set using APU},
	journal = {IJCA Special Issue on International Conference on Computing, Communication and Sensor Network},
	year = {2013},
	volume = {CCSN2012},
	number = {2},
	pages = {19-23},
	month = {March},
	note = {Full text available}
}

Abstract

This paper includes User Defined Instruction Decoding using the Auxiliary Processor Unit (APU) controller which allows the designer to extend the native PowerPC 405 instruction set with custom instructions that are executed by an FPGA Fabric Co-processor Module (FCM) which accelerate the system performance with the APU Controller, with an aim that Portions of certain software applications that are implemented in software can run faster by moving the implementation into hardware. In a Virtex™-4 FX FPGA, the embedded PowerPC™ 405 (PPC405) processor can run software and offload computations to hardware modules in the FPGA. In such a system, a coprocessor interface known as the Auxiliary Processor Unit (APU) is used to transfer data between the processor and the FPGA. Because certain computations can be done more efficiently in software, and others in hardware, an APU-enhanced system results in a faster overall solution for many digital signal processing (DSP) applications.

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