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Analysing the Performance of Multi-core Architecture

IJCA Special Issue on International Conference on Computing, Communication and Sensor Network
© 2013 by IJCA Journal
CCSN2012 - Number 4
Year of Publication: 2013
Ram Prasad Mohanty
Ashok Kumar Turuk
Bibhudatta Sahoo

Ram Prasad Mohanty, Ashok Kumar Turuk and Bibhudatta Sahoo. Article: Analysing the Performance of Multi-core Architecture. IJCA Special Issue on International Conference on Computing, Communication and Sensor Network CCSN2012(4):28-33, March 2013. Full text available. BibTeX

	author = {Ram Prasad Mohanty and Ashok Kumar Turuk and Bibhudatta Sahoo},
	title = {Article: Analysing the Performance of Multi-core Architecture},
	journal = {IJCA Special Issue on International Conference on Computing, Communication and Sensor Network},
	year = {2013},
	volume = {CCSN2012},
	number = {4},
	pages = {28-33},
	month = {March},
	note = {Full text available}


The advancement in technology has brought immense amount of changes in the design and productivity of applications designed for being used in the personal computers. By implementing greater number of cores to the same chip also results in facing challenges. In this case the challenge that is being faced is the core to core communication as well as the memory in addition to cache coherence. This paper presents a detailed analysis on performance of FFT a divide and conquer algorithm across with the Multi-core architecture with Internal and external network. The architectures are being defined using memory configuration and context configuration with help of Multi2Sim 3. 4 simulator. The performance of these architectures have been simulated with Splash 2 Benchmark.


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