Call for Paper - July 2022 Edition
IJCA solicits original research papers for the July 2022 Edition. Last date of manuscript submission is June 20, 2022. Read More

Effect of Line Parasitic Variations on Propagation Delay in Global VLSI Interconnects

Print
PDF
Evolution in Networks and Computer Communications
© 2011 by IJCA Journal
Number 1 - Article 1
Year of Publication: 2011
Authors:
K. G. Verma
Raghuvir Singh
B. K. Kaushik
Brijesh Kumar

K G Verma, Raghuvir Singh, B K Kaushik and Brijesh Kumar. Effect of Line Parasitic Variations on Propagation Delay in Global VLSI Interconnects. IJCA Special Issue on Evolution in Networks and Computer Communications (1):1-6, 2011. Full text available. BibTeX

@article{key:article,
	author = {K. G. Verma and Raghuvir Singh and B. K. Kaushik and Brijesh Kumar},
	title = {Effect of Line Parasitic Variations on Propagation Delay in Global VLSI Interconnects},
	journal = {IJCA Special Issue on Evolution in Networks and Computer Communications},
	year = {2011},
	number = {1},
	pages = {1-6},
	note = {Full text available}
}

Abstract

Process variation is considered to be a major concern in the design of circuits including interconnect pipelines in current deep submicron regime. Process variation results in uncertainties of circuit performances such as propagation delay. The performance of VLSI/ULSI chip is becoming less predictable as device dimensions shrinks below the sub-100-nm scale. The reduced predictability can be attributed to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. The interconnect line resistance and capacitance varies due to changes in interconnect width and thickness, substrate, implant impurity level, and surface charge. This paper provides an analysis of the effect of interconnect parasitic variation on the propagation delay through driver-interconnect-load (DIL) system. The impact of process induced variations on propagation delay of the circuit is discussed for three different fabrication technologies i.e. 130nm, 70nm and 45nm. The comparison between three technologies interestingly shows that the effect of line resistive and capacitive parasitic variation on propagation delay has almost uniform trend as feature size shrinks. However, resistive parasitic variation in global interconnects has very nominal effect on the propagation delay as compared to capacitive parasitic. Propagation delay variation is from 0.01% to 0.04% and -4.32% to 18.1 % due to resistive and capacitive deviation of -6.1% to 25% respectively.

Reference

  1. Mizuno, T., Okumtura, J. and Toriumi, A. 1994. Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET’s. IEEE Trans. Electron Devices, vol. 41, no. 11 (Nov. 1994) 2216–2221.
  2. Frank, D., Dennard, R., Nowak, E., Solomon, P., Taur, Y. and Wong, H. S. 2001. Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE, vol. 89, no. 3 (Mar. 2001) 259–288.
  3. Croon, J., Decoutere, S., Sansen, W. and Maes, H. 2004 Physical modeling and prediction of the matching properties of MOSFETs. Proc. 34th European Solid-State Device Research Conference (ESSDERC), 193–196.
  4. “The International Technology Roadmap for Semiconductors,” ITRS Website. [Online]. Available: http://public.itrs.net.
  5. Kaushik, Brajesh Kumar, Sarkar, Sankar and Agarwal, R. P. 2007. Waveform Analysis and Delay Prediction for a CMOS Gate Driving RLC Interconnect Load. Integration, the VLSI Journal, Elsevier Pub. Netherlands, vol. 40, no. 4 (July 2007) 394-405.
  6. Kaushik, Brajesh Kumar, Sarkar, Sankar and Agarwal, R. P. 2008. Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems. vol. 27, no. 6 (June 2008) 1150-1154.
  7. Kaushik, Brajesh Kumar, Sarkar, Sankar and Agarwal, R. P. and Joshi, Ramesh C. 2009. Crosstalk Analysis of Simultaneously Switching Interconnects. International Journal of Electronics, Taylor and Francis (UK), vol. 96, no.10 (October 2009) 1095-1114.
  8. Kaushik, Brajesh Kumar, Sarkar, Sankar and Agarwal, R. P. and Joshi, Ramesh C. 2007. Effect of Line Resistance and Driver Width on Crosstalk in Coupled VLSI Interconnects. Microelectronics International, Emerald Pub. U.K., Vol. 24, no. 3 (August 2007) 42-45.
  9. F. Kreupl, A. P. Graham, G. S. Deusberg, W. Steinhogl, M. Liebau, E. Unger, and W. Honlein, “Carbon Nanotubes in Interconnect Applications,” Proc. Microelectronics Engineering, vol. 64, no. 1-4, pp. 399-408, Oct. 2002.
  10. A. K. Goel, High-speed VLSI Interconnections, Wiley-IEEE Press, Sep. 2007.
  11. A. K. Geol, “Nanotube and other interconnects for nanotechnology circuits,” Proc. Electrical and Computer Engineering, 2008, pp. 000189-000192, May 2008.
  12. Masuda, H., Ohkawa, S., Kurokawa, A. and Aoki, M. 2005 Challenge: Variability characterization and modeling for 65 to 90 nm processes. Proc. CICC 593–599.
  13. Boning, D. and Nassif, S. 2001. Models of process variations in device and interconnect. Design of High Performance Microprocessor Circuits, Chandrakasan, A., Bowhill, W. J. and Fox, F. Eds. New York: Wiley, 2001.
  14. Verma, K. G., Kaushik, B. K. and Singh, R. 2009. Effects of Process Variation in VLSI Interconnects: a Technical Review. Microelectronics International, Emerald Pub. U. K., Vol. 26, no. 3, (2009) 49-55.
  15. Jarrar, A. and Taylor, K. 2006 On-Chip Variation and Timing Closure. Electronics Design, Strategy, News (EDN), June, 2006.
  16. Verma, K. G. and Kaushik, B. K. 2010. Effect of Process Based Oxide Thickness Variation on the Delay of DIL System Using Monte Carlo Analysis. International Journal of Recent Trends in Engineering. Academy Publishers, Finland, Vol. 3, no. 4 (2010.) 27--31
  17. Verma, K. G., Kaushik, B. K. and Singh, R. 2010. Propagation Delay Variations under Process Deviation in Driver Interconnect Load System," International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom), (Oct 2010) 408-410.
  18. Verma, K. G., Kaushik, B. K. and Singh, Raghuvir. 2010. Propagation Delay Variation due to Process Induced Threshold Voltage Variation. Communications in Computer and Information Science, 1, Information and Communication Technologies, Springer, vol. 101, Part 3, (2010) 520-524.
  19. Verma, K. G., Kaushik, B. K. and Singh, Raghuvir. 2011. Monte Carlo Analysis of Propagation Delay Deviation due to Process Induced Line Parasitic Variations in Global VLSI Interconnects. International Journal of Computer Applications. April 2011.
  20. Mehrotra, V., Nassif, S., Boning, D., and Chung, J. 1998. Modeling the Effect of Manufacturing Variation on High-Speed Microprocessor Interconnect Performance. IEEE International Electron Devices Meeting (IEDM), (June, 1998) 767-770.
  21. Harper, C. A. 2002. Electronic Assembly Fabrication: Chips Circuits Boards, Packages, and Components, McGraw- Hill (Maryland).
  22. Verma, K. G., and Singh, Raghuvir, Kaushik, B. K. and Kumar, Brijesh. 2011. Monte Carlo Analysis of Propagation Delay due to Process Induced Line Parasitic Variations in VLSI Interconnects. Proc. IEEE Int. Conf. on International Conference on Networks and Computer Communications (ETNCC2011), (April 2011) 6-10.
  23. Verma, K. G., Kaushik, B. K. and Singh, Raghuvir, 2011. Monte Carlo Analysis of Propagation Delay Deviation due to Process Induced Line Parasitic Variations in Global VLSI Interconnects. International Journal of Computer Applications Vol.20, no.1, (April 2011) 0975 – 8887.