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Escape Path based Irregular Network-on-chip Simulation Framework

Evolution in Networks and Computer Communications
© 2011 by IJCA Journal
Number 1 - Article 2
Year of Publication: 2011
Naveen Choudhary
M. S. Gaur
V. Laxmi

Naveen Choudhary, M S Gaur and V Laxmi. Escape Path based Irregular Network-on-chip Simulation Framework. IJCA Special Issue on Evolution in Networks and Computer Communications (1):7-12, 2011. Full text available. BibTeX

	author = {Naveen Choudhary and M. S. Gaur and V. Laxmi},
	title = {Escape Path based Irregular Network-on-chip Simulation Framework},
	journal = {IJCA Special Issue on Evolution in Networks and Computer Communications},
	year = {2011},
	number = {1},
	pages = {7-12},
	note = {Full text available}


Network-on-Chip(NoC) has been proposed as a solution for addressing the communication infrastructure design challenges of future high-performance nanoscale architecture of SoCs. IrNIRGAM is a discrete event, cycle accurate simulator targeted at irregular topology based Network on Chip (NoC) research. The generic, modular, and extensible framework of IrNIRGAM provides substantial support to experiment with direct network based NoC designs in terms of routing algorithms, applications on various topologies and related performance parameters such as throughput, communication latency etc. IrNIRGAM is written in SystemC and C++. Topology represents the most important characteristic of NoC architectures and essentially defines the physical interconnection of the router nodes. In IrNIRGAM, input buffered routers can have multiple virtual channels (VCs) and uses wormhole switching for flow control. The packets are split into an arbitrary number of flits (flow control units) and forwarded through the network in a pipelined fashion. A Round-Robin scheme for switch arbitration is used in the router nodes to provide fair bandwidth allocation while effectively preventing scheduling anomalies like starvation.


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