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Design of a 4-bit 2’s Complement Reversible Circuit for Arithmetic Logic Unit Applications

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IJCA Special Issue on International Conference on Communication, Computing and Information Technology
© 2013 by IJCA Journal
ICCCMIT - Number 2
Year of Publication: 2013
Authors:
Vandana Shukla
O. P. Singh
G. R. Mishra
R. K. Tiwari

Vandana Shukla, O P Singh, G R Mishra and R K Tiwari. Article: Design of a 4-bit 2s Complement Reversible Circuit for Arithmetic Logic Unit Applications. IJCA Special Issue on International Conference on Communication, Computing and Information Technology ICCCMIT(2):1-5, February 2013. Full text available. BibTeX

@article{key:article,
	author = {Vandana Shukla and O. P. Singh and G. R. Mishra and R. K. Tiwari},
	title = {Article: Design of a 4-bit 2s Complement Reversible Circuit for Arithmetic Logic Unit Applications},
	journal = {IJCA Special Issue on International Conference on Communication, Computing and Information Technology},
	year = {2013},
	volume = {ICCCMIT},
	number = {2},
	pages = {1-5},
	month = {February},
	note = {Full text available}
}

Abstract

Nowadays reversible circuit designing is the emerging area of research. This design strategy aims towards the formation of digital circuits with ideally zero power dissipation. In this paper we have proposed a new reversible logic module to design a 4-bit binary 2's complement circuit. This complement circuit using reversible logic can be used to design other low loss Arithmetic circuit. Proposed circuits have been simulated using ModelSim and implemented using Xilinx Spartan2 FPGA platform.

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