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Design and Realization of FPGA based Off-Chip Trained MLP for Classical XOR Problem and Need of On-Chip Training

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IJCA Special Issue on International Conference on Electronics, Communication and Information systems
© 2012 by IJCA Journal
ICECI - Number 2
Year of Publication: 2012
Authors:
K. Packia Lakshmi
M. Subadra

Packia K Lakshmi and M Subadra. Article: Design and Realization of FPGA based Off-Chip Trained MLP for Classical XOR Problem and Need of On-Chip Training. IJCA Special Issue on International Conference on Electronics, Communication and Information systems ICECI(2):7-12, November 2012. Full text available. BibTeX

@article{key:article,
	author = {K. Packia Lakshmi and M. Subadra},
	title = {Article: Design and Realization of FPGA based Off-Chip Trained MLP for Classical XOR Problem and Need of On-Chip Training},
	journal = {IJCA Special Issue on International Conference on Electronics, Communication and Information systems},
	year = {2012},
	volume = {ICECI},
	number = {2},
	pages = {7-12},
	month = {November},
	note = {Full text available}
}

Abstract

The main intension of this work is to present the importance of neural chip with learning capability. The designed sequentially trained MLP structure is used to solve the classical XOR problem and the structure is realized on FPGA device environment. By comparing the device utilization summary for the design in different families of Xilinx FPGA, the importance of platform selection for hardware implementation is presented. Finally the importance of on-chip learning is emphasized.

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